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Tobias Diedrich7a952042017-12-03 10:09:28 +01001/*
2 * This file is part of the coreboot project.
3 *
Tobias Diedrich7a952042017-12-03 10:09:28 +01004 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of
8 * the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <stdint.h>
17#include <northbridge/intel/sandybridge/sandybridge.h>
Julius Wernercd49cce2019-03-05 16:53:33 -080018#if CONFIG(USE_NATIVE_RAMINIT)
Tobias Diedrich7a952042017-12-03 10:09:28 +010019#include <northbridge/intel/sandybridge/raminit_native.h>
20#else
21#include <northbridge/intel/sandybridge/raminit.h>
22#endif
Patrick Rudolphda9302a2019-03-24 17:01:41 +010023#include <southbridge/intel/bd82x6x/pch.h>
Tobias Diedrich7a952042017-12-03 10:09:28 +010024
Julius Wernercd49cce2019-03-05 16:53:33 -080025#if !CONFIG(USE_NATIVE_RAMINIT)
Tobias Diedrich7a952042017-12-03 10:09:28 +010026void mainboard_fill_pei_data(struct pei_data *pei_data)
27{
28 struct pei_data pei_data_template = {
29 .pei_version = PEI_VERSION,
30 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
31 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
32 .epbar = DEFAULT_EPBAR,
33 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
34 .smbusbar = SMBUS_IO_BASE,
35 .wdbbar = 0x4000000,
36 .wdbsize = 0x1000,
37 .hpet_address = CONFIG_HPET_ADDRESS,
38 .rcba = (uintptr_t)DEFAULT_RCBABASE,
39 .pmbase = DEFAULT_PMBASE,
40 .gpiobase = DEFAULT_GPIOBASE,
41 .thermalbase = 0xfed08000,
42 .system_type = 0, // 0 Mobile, 1 Desktop/Server
43 .tseg_size = CONFIG_SMM_TSEG_SIZE,
44 .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
45 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
46 .ec_present = 0,
47 .gbe_enable = 1,
48 // 0 = leave channel enabled
49 // 1 = disable dimm 0 on channel
50 // 2 = disable dimm 1 on channel
51 // 3 = disable dimm 0+1 on channel
52 .dimm_channel0_disabled = 2,
53 .dimm_channel1_disabled = 2,
54 .max_ddr3_freq = 1333,
55 .usb_port_config = {
56#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
57#include "usb.h"
58 },
59 };
60 *pei_data = pei_data_template;
61}
62
63int mainboard_should_reset_usb(int s3resume)
64{
65 return !s3resume;
66}
67#endif