Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 21 | #include <arch/io.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 30 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 31 | #include <southbridge/intel/bd82x6x/pch.h> |
| 32 | #include <southbridge/intel/bd82x6x/gpio.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 33 | #include <arch/cpu.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 34 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 35 | #include <halt.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 36 | #if CONFIG_CHROMEOS |
| 37 | #include <vendorcode/google/chromeos/chromeos.h> |
| 38 | #endif |
| 39 | #include <cbfs.h> |
| 40 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 41 | void pch_enable_lpc(void) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 42 | { |
| 43 | /* EC Decode Range Port60/64 and Port62/66 */ |
| 44 | /* Enable EC and PS/2 Keyboard/Mouse*/ |
| 45 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); |
| 46 | |
| 47 | /* EC Decode Range Port68/6C */ |
| 48 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001); |
| 49 | |
| 50 | /* EC Decode Range Port 380-387 */ |
| 51 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001); |
| 52 | |
| 53 | } |
| 54 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 55 | void rcba_config(void) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 56 | { |
| 57 | u32 reg32; |
| 58 | |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 59 | /* |
| 60 | * GFX INTA -> PIRQA (MSI) |
| 61 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 62 | * D28IP_P2IP ETH0 INTB -> PIRQF |
| 63 | * D28IP_P3IP SDCARD INTC -> PIRQD |
| 64 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 65 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 66 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 67 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 68 | * D31IP_TTIP THRT INTC -> PIRQA |
| 69 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 70 | * |
| 71 | * Trackpad interrupt is edge triggered and cannot be shared. |
| 72 | * TRACKPAD -> PIRQG |
| 73 | |
| 74 | */ |
| 75 | |
| 76 | /* Device interrupt pin register (board specific) */ |
| 77 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 78 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 79 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 80 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| 81 | (INTC << D28IP_P3IP); |
| 82 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 83 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 84 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 85 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 86 | |
| 87 | /* Device interrupt route registers */ |
| 88 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 89 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 90 | DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| 91 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 92 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 93 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 94 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 95 | |
| 96 | /* Enable IOAPIC (generic) */ |
| 97 | RCBA16(OIC) = 0x0100; |
| 98 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 99 | (void) RCBA16(OIC); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 100 | |
| 101 | /* Disable unused devices (board specific) */ |
| 102 | reg32 = RCBA32(FD); |
| 103 | reg32 |= PCH_DISABLE_ALWAYS; |
| 104 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 105 | reg32 |= PCH_DISABLE_P2P; |
| 106 | RCBA32(FD) = reg32; |
| 107 | } |
| 108 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 109 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 110 | /* enabled usb oc pin length */ |
| 111 | { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ |
| 112 | { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ |
| 113 | { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ |
| 114 | { 0, 0, 0x0000 }, /* P3: Empty */ |
| 115 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 116 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 117 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 118 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 119 | { 0, 4, 0x0000 }, /* P8: Empty */ |
| 120 | { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ |
| 121 | { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ |
| 122 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 123 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 124 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 125 | }; |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 126 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 127 | void mainboard_get_spd(spd_raw_data *spd) { |
| 128 | read_spd(&spd[0], 0x50); |
| 129 | read_spd(&spd[2], 0x52); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 130 | } |