Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/amd/picasso |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 4 | # ACP Configuration |
| 5 | register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA" |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 6 | |
| 7 | # Set FADT Configuration |
Raul E Rangel | 1c88b10 | 2021-02-11 10:35:32 -0700 | [diff] [blame] | 8 | register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" |
| 9 | register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 10 | |
| 11 | register "emmc_config" = "{ |
| 12 | .timing = SD_EMMC_DISABLE, |
| 13 | }" |
| 14 | |
| 15 | register "has_usb2_phy_tune_params" = "1" |
| 16 | |
| 17 | # Controller0 Port0 Default |
| 18 | register "usb_2_port_tune_params[0]" = "{ |
| 19 | .com_pds_tune = 0x03, |
| 20 | .sq_rx_tune = 0x3, |
| 21 | .tx_fsls_tune = 0x3, |
| 22 | .tx_pre_emp_amp_tune = 0x03, |
| 23 | .tx_pre_emp_pulse_tune = 0x0, |
| 24 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 25 | .tx_vref_tune = 0x6, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 26 | .tx_hsxv_tune = 0x3, |
| 27 | .tx_res_tune = 0x01, |
| 28 | }" |
| 29 | |
| 30 | # Controller0 Port1 Default |
| 31 | register "usb_2_port_tune_params[1]" = "{ |
| 32 | .com_pds_tune = 0x03, |
| 33 | .sq_rx_tune = 0x3, |
| 34 | .tx_fsls_tune = 0x3, |
| 35 | .tx_pre_emp_amp_tune = 0x03, |
| 36 | .tx_pre_emp_pulse_tune = 0x0, |
| 37 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 38 | .tx_vref_tune = 0x6, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 39 | .tx_hsxv_tune = 0x3, |
| 40 | .tx_res_tune = 0x01, |
| 41 | }" |
| 42 | |
| 43 | # Controller0 Port2 Default |
| 44 | register "usb_2_port_tune_params[2]" = "{ |
| 45 | .com_pds_tune = 0x03, |
| 46 | .sq_rx_tune = 0x3, |
| 47 | .tx_fsls_tune = 0x3, |
| 48 | .tx_pre_emp_amp_tune = 0x03, |
| 49 | .tx_pre_emp_pulse_tune = 0x0, |
| 50 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 51 | .tx_vref_tune = 0x6, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 52 | .tx_hsxv_tune = 0x3, |
| 53 | .tx_res_tune = 0x01, |
| 54 | }" |
| 55 | |
| 56 | # Controller0 Port3 Default |
| 57 | register "usb_2_port_tune_params[3]" = "{ |
| 58 | .com_pds_tune = 0x03, |
| 59 | .sq_rx_tune = 0x3, |
| 60 | .tx_fsls_tune = 0x3, |
| 61 | .tx_pre_emp_amp_tune = 0x03, |
| 62 | .tx_pre_emp_pulse_tune = 0x0, |
| 63 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 64 | .tx_vref_tune = 0x6, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 65 | .tx_hsxv_tune = 0x3, |
| 66 | .tx_res_tune = 0x01, |
| 67 | }" |
| 68 | |
| 69 | # Controller0 Port4 Default |
| 70 | register "usb_2_port_tune_params[4]" = "{ |
| 71 | .com_pds_tune = 0x03, |
| 72 | .sq_rx_tune = 0x3, |
| 73 | .tx_fsls_tune = 0x3, |
| 74 | .tx_pre_emp_amp_tune = 0x02, |
| 75 | .tx_pre_emp_pulse_tune = 0x0, |
| 76 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 77 | .tx_vref_tune = 0x5, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 78 | .tx_hsxv_tune = 0x3, |
| 79 | .tx_res_tune = 0x01, |
| 80 | }" |
| 81 | |
| 82 | # Controller0 Port5 Default |
| 83 | register "usb_2_port_tune_params[5]" = "{ |
| 84 | .com_pds_tune = 0x03, |
| 85 | .sq_rx_tune = 0x3, |
| 86 | .tx_fsls_tune = 0x3, |
| 87 | .tx_pre_emp_amp_tune = 0x02, |
| 88 | .tx_pre_emp_pulse_tune = 0x0, |
| 89 | .tx_rise_tune = 0x1, |
Kevin Chiu | de20b28 | 2020-11-19 14:09:47 +0800 | [diff] [blame] | 90 | .tx_vref_tune = 0x5, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 91 | .tx_hsxv_tune = 0x3, |
| 92 | .tx_res_tune = 0x01, |
| 93 | }" |
| 94 | |
| 95 | # USB OC pin mapping; all ports share one OC pin |
| 96 | register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" |
| 97 | register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" |
| 98 | register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" |
| 99 | register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" |
| 100 | register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" |
| 101 | register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" |
| 102 | |
| 103 | # SPI Configuration |
| 104 | register "common_config.spi_config" = "{ |
| 105 | .normal_speed = SPI_SPEED_33M, /* MHz */ |
| 106 | .fast_speed = SPI_SPEED_66M, /* MHz */ |
| 107 | .altio_speed = SPI_SPEED_33M, /* MHz */ |
| 108 | .tpm_speed = SPI_SPEED_33M, /* MHz */ |
| 109 | .read_mode = SPI_READ_MODE_QUAD114, |
| 110 | }" |
| 111 | |
| 112 | # eSPI Configuration |
| 113 | register "common_config.espi_config" = "{ |
| 114 | .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, |
| 115 | .generic_io_range[0] = { |
| 116 | .base = 0x662, |
| 117 | .size = 8, |
| 118 | }, |
| 119 | |
| 120 | .io_mode = ESPI_IO_MODE_SINGLE, |
| 121 | .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, |
| 122 | .crc_check_enable = 1, |
Raul E Rangel | 8317e72 | 2021-05-05 13:38:27 -0600 | [diff] [blame] | 123 | .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 124 | .periph_ch_en = 0, |
| 125 | .vw_ch_en = 0, |
| 126 | .oob_ch_en = 0, |
| 127 | .flash_ch_en = 0, |
| 128 | }" |
| 129 | |
| 130 | # genral purpose PCIe clock output configuration |
| 131 | register "gpp_clk_config[0]" = "GPP_CLK_REQ" |
| 132 | register "gpp_clk_config[1]" = "GPP_CLK_REQ" |
| 133 | register "gpp_clk_config[2]" = "GPP_CLK_REQ" |
| 134 | register "gpp_clk_config[3]" = "GPP_CLK_OFF" |
| 135 | register "gpp_clk_config[4]" = "GPP_CLK_REQ" |
| 136 | register "gpp_clk_config[5]" = "GPP_CLK_OFF" |
| 137 | register "gpp_clk_config[6]" = "GPP_CLK_OFF" |
| 138 | |
Felix Held | f3819bd | 2021-05-25 21:20:00 +0200 | [diff] [blame] | 139 | register "pspp_policy" = "DXIO_PSPP_BALANCED" |
Felix Held | 0fec867 | 2021-05-25 21:07:23 +0200 | [diff] [blame] | 140 | |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 141 | device domain 0 on |
| 142 | subsystemid 0x1022 0x1510 inherit |
Felix Held | 4fbab54 | 2021-05-31 19:44:46 +0200 | [diff] [blame] | 143 | device ref iommu on end |
| 144 | device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip |
| 145 | device ref internal_bridge_a on |
Felix Held | 5fd63bd | 2021-05-31 20:07:02 +0200 | [diff] [blame^] | 146 | device ref gfx on end # Internal GPU |
| 147 | device ref gfx_hda on end # Display HDA |
| 148 | device ref crypto on end # Crypto Coprocessor |
| 149 | device ref xhci_0 on end # USB 3.1 |
| 150 | device ref xhci_1 off end # USB 3.1 |
| 151 | device ref acp on end # Audio |
| 152 | device ref hda on end # HDA |
| 153 | device ref mp2 on end # non-Sensor Fusion Hub device |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 154 | end |
Felix Held | 4fbab54 | 2021-05-31 19:44:46 +0200 | [diff] [blame] | 155 | device ref internal_bridge_b on |
Felix Held | 5fd63bd | 2021-05-31 20:07:02 +0200 | [diff] [blame^] | 156 | device ref sata off end # AHCI |
| 157 | device ref xgbe_0 off end # integrated Ethernet MAC |
| 158 | device ref xgbe_1 off end # integrated Ethernet MAC |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 159 | end |
Felix Held | 4fbab54 | 2021-05-31 19:44:46 +0200 | [diff] [blame] | 160 | device ref lpc_bridge on |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 161 | chip superio/smsc/sio1036 # optional debug card |
| 162 | end |
| 163 | end |
Felix Held | 407b866 | 2020-06-23 01:14:46 +0200 | [diff] [blame] | 164 | end # domain |
| 165 | |
| 166 | device mmio 0xfedc9000 on end # UART0 |
| 167 | device mmio 0xfedca000 on end # UART1 |
| 168 | device mmio 0xfedce000 off end # UART2 |
| 169 | device mmio 0xfedcf000 off end # UART3 |
| 170 | |
| 171 | end # chip soc/amd/picasso |