blob: 711ef4d6a1e8db4e8a993ce4ada0ac62e8bafb14 [file] [log] [blame]
Stefan Reinauer6651da32012-04-27 23:16:30 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20# -----------------------------------------------------------------
21entries
22
23#start-bit length config config-ID name
24#0 8 r 0 seconds
25#8 8 r 0 alarm_seconds
26#16 8 r 0 minutes
27#24 8 r 0 alarm_minutes
28#32 8 r 0 hours
29#40 8 r 0 alarm_hours
30#48 8 r 0 day_of_week
31#56 8 r 0 day_of_month
32#64 8 r 0 month
33#72 8 r 0 year
34# -----------------------------------------------------------------
35# Status Register A
36#80 4 r 0 rate_select
37#84 3 r 0 REF_Clock
38#87 1 r 0 UIP
39# -----------------------------------------------------------------
40# Status Register B
41#88 1 r 0 auto_switch_DST
42#89 1 r 0 24_hour_mode
43#90 1 r 0 binary_values_enable
44#91 1 r 0 square-wave_out_enable
45#92 1 r 0 update_finished_enable
46#93 1 r 0 alarm_interrupt_enable
47#94 1 r 0 periodic_interrupt_enable
48#95 1 r 0 disable_clock_updates
49# -----------------------------------------------------------------
50# Status Register C
51#96 4 r 0 status_c_rsvd
52#100 1 r 0 uf_flag
53#101 1 r 0 af_flag
54#102 1 r 0 pf_flag
55#103 1 r 0 irqf_flag
56# -----------------------------------------------------------------
57# Status Register D
58#104 7 r 0 status_d_rsvd
59#111 1 r 0 valid_cmos_ram
60# -----------------------------------------------------------------
61# Diagnostic Status Register
62#112 8 r 0 diag_rsvd1
63
64# -----------------------------------------------------------------
650 120 r 0 reserved_memory
66#120 264 r 0 unused
67
68# -----------------------------------------------------------------
69# RTC_BOOT_BYTE (coreboot hardcoded)
70384 1 e 4 boot_option
71385 1 e 4 last_boot
72388 4 r 0 reboot_bits
73#390 2 r 0 unused?
74
75# -----------------------------------------------------------------
76# coreboot config options: console
77392 3 e 5 baud_rate
78395 4 e 6 debug_level
79#399 1 r 0 unused
80
81# coreboot config options: cpu
82400 1 e 2 hyper_threading
83#401 7 r 0 unused
84
85# coreboot config options: southbridge
86408 1 e 1 nmi
87409 2 e 7 power_on_after_fail
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +010088411 1 e 8 sata_mode
89#412 4 r 0 unused
Stefan Reinauer6651da32012-04-27 23:16:30 +020090
91# coreboot config options: bootloader
92#Used by ChromeOS:
93416 128 r 0 vbnv
Vladimir Serbinenko5fc04d12014-08-03 01:59:38 +020094
95# coreboot config options: northbridge
96544 3 e 11 gfx_uma_size
97
98#547 437 r 0 unused
Stefan Reinauer6651da32012-04-27 23:16:30 +020099
100# SandyBridge MRC Scrambler Seed values
101896 32 r 0 mrc_scrambler_seed
102928 32 r 0 mrc_scrambler_seed_s3
103
104# coreboot config options: check sums
105984 16 h 0 check_sum
106#1000 24 r 0 amd_reserved
107
108# -----------------------------------------------------------------
109
110enumerations
111
112#ID value text
1131 0 Disable
1141 1 Enable
1152 0 Enable
1162 1 Disable
1174 0 Fallback
1184 1 Normal
1195 0 115200
1205 1 57600
1215 2 38400
1225 3 19200
1235 4 9600
1245 5 4800
1255 6 2400
1265 7 1200
1276 1 Emergency
1286 2 Alert
1296 3 Critical
1306 4 Error
1316 5 Warning
1326 6 Notice
1336 7 Info
1346 8 Debug
1356 9 Spew
1367 0 Disable
1377 1 Enable
1387 2 Keep
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +01001398 0 AHCI
1408 1 Compatible
Vladimir Serbinenko5fc04d12014-08-03 01:59:38 +020014111 0 32M
14211 1 64M
14311 2 96M
14411 3 128M
14511 4 160M
14611 5 192M
14711 6 224M
148
Stefan Reinauer6651da32012-04-27 23:16:30 +0200149# -----------------------------------------------------------------
150checksums
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152checksum 392 415 984