Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
| 18 | #include <arch/early_variables.h> |
| 19 | #include <console/console.h> |
| 20 | #include <cbfs.h> |
| 21 | #include "../chip.h" |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 22 | #include <fsp/memmap.h> |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 23 | #include <fsp/util.h> |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 24 | #include <soc/pci_devs.h> |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 25 | #include <soc/QuarkNcSocId.h> |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 26 | #include <soc/romstage.h> |
| 27 | #include <string.h> |
| 28 | |
| 29 | asmlinkage void *car_stage_c_entry(void) |
| 30 | { |
| 31 | FSP_INFO_HEADER *fih; |
| 32 | struct cache_as_ram_params car_params = {0}; |
| 33 | void *top_of_stack; |
| 34 | |
| 35 | post_code(0x20); |
| 36 | |
| 37 | /* Copy the FSP binary into ESRAM */ |
| 38 | memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, |
| 39 | 0x00040000); |
| 40 | |
| 41 | /* Locate the FSP header in ESRAM */ |
| 42 | fih = find_fsp(CONFIG_FSP_ESRAM_LOC); |
| 43 | |
| 44 | /* Start the early verstage/romstage code */ |
| 45 | post_code(0x2A); |
| 46 | car_params.fih = fih; |
| 47 | top_of_stack = cache_as_ram_main(&car_params); |
| 48 | |
| 49 | /* Initialize MTRRs and switch stacks after RAM initialized */ |
| 50 | return top_of_stack; |
| 51 | } |
| 52 | |
| 53 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 54 | |
| 55 | struct chipset_power_state *get_power_state(void) |
| 56 | { |
| 57 | return (struct chipset_power_state *)car_get_var_ptr(&power_state); |
| 58 | } |
| 59 | |
| 60 | struct chipset_power_state *fill_power_state(void) |
| 61 | { |
| 62 | struct chipset_power_state *ps = get_power_state(); |
| 63 | |
| 64 | ps->prev_sleep_state = 0; |
| 65 | printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 66 | return ps; |
| 67 | } |
| 68 | |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 69 | size_t mmap_region_granularity(void) |
| 70 | { |
| 71 | /* Align to 8 MiB by default */ |
| 72 | return 8 << 20; |
| 73 | } |
| 74 | |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 75 | /* Initialize the UPD parameters for MemoryInit */ |
| 76 | void soc_memory_init_params(struct romstage_params *params, |
| 77 | MEMORY_INIT_UPD *upd) |
| 78 | { |
| 79 | const struct device *dev; |
| 80 | const struct soc_intel_quark_config *config; |
| 81 | char *rmu_file; |
| 82 | size_t rmu_file_len; |
| 83 | |
| 84 | /* Locate the configuration data from devicetree.cb */ |
| 85 | dev = dev_find_slot(0, LPC_DEV_FUNC); |
| 86 | if (!dev) { |
| 87 | printk(BIOS_CRIT, |
| 88 | "Error! Device (PCI:0:%02x.%01x) not found, " |
| 89 | "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, |
| 90 | PCI_FUNCTION_NUMBER_QNC_LPC); |
| 91 | return; |
| 92 | } |
| 93 | config = dev->chip_info; |
| 94 | |
| 95 | /* Clear SMI and wake events */ |
| 96 | clear_smi_and_wake_events(); |
| 97 | |
| 98 | /* Locate the RMU data file in flash */ |
| 99 | rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, |
| 100 | &rmu_file_len); |
| 101 | if (!rmu_file) |
| 102 | die("Microcode file (rmu.bin) not found."); |
| 103 | |
| 104 | /* Update the UPD data for MemoryInit */ |
| 105 | upd->AddrMode = config->AddrMode; |
| 106 | upd->ChanMask = config->ChanMask; |
| 107 | upd->ChanWidth = config->ChanWidth; |
| 108 | upd->DramDensity = config->DramDensity; |
| 109 | upd->DramRonVal = config->DramRonVal; |
| 110 | upd->DramRttNomVal = config->DramRttNomVal; |
| 111 | upd->DramRttWrVal = config->DramRttWrVal; |
| 112 | upd->DramSpeed = config->DramSpeed; |
| 113 | upd->DramType = config->DramType; |
| 114 | upd->DramWidth = config->DramWidth; |
| 115 | upd->EccScrubBlkSize = config->EccScrubBlkSize; |
| 116 | upd->EccScrubInterval = config->EccScrubInterval; |
| 117 | upd->Flags = config->Flags; |
| 118 | upd->FspReservedMemoryLength = config->FspReservedMemoryLength; |
| 119 | upd->RankMask = config->RankMask; |
| 120 | upd->RmuBaseAddress = (uintptr_t)rmu_file; |
| 121 | upd->RmuLength = rmu_file_len; |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame^] | 122 | upd->SerialPortWriteChar = console_log_level(BIOS_SPEW) |
| 123 | ? (uintptr_t)fsp_write_line : 0; |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 124 | upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? |
| 125 | config->SmmTsegSize : 0; |
| 126 | upd->SocRdOdtVal = config->SocRdOdtVal; |
| 127 | upd->SocWrRonVal = config->SocWrRonVal; |
| 128 | upd->SocWrSlewRate = config->SocWrSlewRate; |
| 129 | upd->SrInt = config->SrInt; |
| 130 | upd->SrTemp = config->SrTemp; |
| 131 | upd->tCL = config->tCL; |
| 132 | upd->tFAW = config->tFAW; |
| 133 | upd->tRAS = config->tRAS; |
| 134 | upd->tRRD = config->tRRD; |
| 135 | upd->tWTR = config->tWTR; |
| 136 | } |
| 137 | |
| 138 | void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |
| 139 | MEMORY_INIT_UPD *new) |
| 140 | { |
| 141 | /* Display the parameters for MemoryInit */ |
| 142 | printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); |
| 143 | fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), |
| 144 | old->AddrMode, new->AddrMode); |
| 145 | fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), |
| 146 | old->ChanMask, new->ChanMask); |
| 147 | fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), |
| 148 | old->ChanWidth, new->ChanWidth); |
| 149 | fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), |
| 150 | old->DramDensity, new->DramDensity); |
| 151 | fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), |
| 152 | old->DramRonVal, new->DramRonVal); |
| 153 | fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), |
| 154 | old->DramRttNomVal, new->DramRttNomVal); |
| 155 | fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), |
| 156 | old->DramRttWrVal, new->DramRttWrVal); |
| 157 | fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), |
| 158 | old->DramSpeed, new->DramSpeed); |
| 159 | fsp_display_upd_value("DramType", sizeof(old->DramType), |
| 160 | old->DramType, new->DramType); |
| 161 | fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), |
| 162 | old->DramWidth, new->DramWidth); |
| 163 | fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), |
| 164 | old->EccScrubBlkSize, new->EccScrubBlkSize); |
| 165 | fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), |
| 166 | old->EccScrubInterval, new->EccScrubInterval); |
| 167 | fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, |
| 168 | new->Flags); |
| 169 | fsp_display_upd_value("FspReservedMemoryLength", |
| 170 | sizeof(old->FspReservedMemoryLength), |
| 171 | old->FspReservedMemoryLength, new->FspReservedMemoryLength); |
| 172 | fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, |
| 173 | new->RankMask); |
| 174 | fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), |
| 175 | old->RmuBaseAddress, new->RmuBaseAddress); |
| 176 | fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), |
| 177 | old->RmuLength, new->RmuLength); |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame^] | 178 | fsp_display_upd_value("SerialPortPollForChar", |
| 179 | sizeof(old->SerialPortPollForChar), |
| 180 | old->SerialPortPollForChar, new->SerialPortPollForChar); |
| 181 | fsp_display_upd_value("SerialPortReadChar", |
| 182 | sizeof(old->SerialPortReadChar), |
| 183 | old->SerialPortReadChar, new->SerialPortReadChar); |
| 184 | fsp_display_upd_value("SerialPortWriteChar", |
| 185 | sizeof(old->SerialPortWriteChar), |
| 186 | old->SerialPortWriteChar, new->SerialPortWriteChar); |
Lee Leahy | 01728bb | 2016-07-20 08:58:58 -0700 | [diff] [blame] | 187 | fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), |
| 188 | old->SmmTsegSize, new->SmmTsegSize); |
| 189 | fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), |
| 190 | old->SocRdOdtVal, new->SocRdOdtVal); |
| 191 | fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), |
| 192 | old->SocWrRonVal, new->SocWrRonVal); |
| 193 | fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), |
| 194 | old->SocWrSlewRate, new->SocWrSlewRate); |
| 195 | fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, |
| 196 | new->SrInt); |
| 197 | fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, |
| 198 | new->SrTemp); |
| 199 | fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); |
| 200 | fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); |
| 201 | fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); |
| 202 | fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); |
| 203 | fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); |
| 204 | } |
| 205 | |
| 206 | void soc_after_ram_init(struct romstage_params *params) |
| 207 | { |
| 208 | /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ |
| 209 | disable_rom_shadow(); |
| 210 | |
| 211 | /* Initialize the PCIe bridges */ |
| 212 | pcie_init(); |
| 213 | } |