Marc Jones | 5dd4a20 | 2009-03-20 16:36:05 +0000 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007 AMD |
| 5 | ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; either version 2 of the License, or |
| 10 | ## (at your option) any later version. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | ## |
| 21 | |
| 22 | uses HAVE_MP_TABLE |
| 23 | uses HAVE_PIRQ_TABLE |
| 24 | uses HAVE_ACPI_TABLES |
| 25 | uses ACPI_SSDTX_NUM |
| 26 | uses USE_FALLBACK_IMAGE |
| 27 | uses USE_FAILOVER_IMAGE |
| 28 | uses HAVE_FALLBACK_BOOT |
| 29 | uses HAVE_FAILOVER_BOOT |
| 30 | uses HAVE_HARD_RESET |
| 31 | uses IRQ_SLOT_COUNT |
| 32 | uses HAVE_OPTION_TABLE |
| 33 | uses CONFIG_MAX_CPUS |
| 34 | uses CONFIG_MAX_PHYSICAL_CPUS |
| 35 | uses CONFIG_LOGICAL_CPUS |
| 36 | uses CONFIG_IOAPIC |
| 37 | uses CONFIG_SMP |
| 38 | uses FALLBACK_SIZE |
| 39 | uses FAILOVER_SIZE |
| 40 | uses ROM_SIZE |
| 41 | uses ROM_SECTION_SIZE |
| 42 | uses ROM_IMAGE_SIZE |
| 43 | uses ROM_SECTION_SIZE |
| 44 | uses ROM_SECTION_OFFSET |
| 45 | uses CONFIG_ROM_PAYLOAD |
| 46 | uses CONFIG_ROM_PAYLOAD_START |
| 47 | uses CONFIG_COMPRESSED_PAYLOAD_NRV2B |
| 48 | uses CONFIG_COMPRESSED_PAYLOAD_LZMA |
| 49 | uses CONFIG_PRECOMPRESSED_PAYLOAD |
| 50 | uses PAYLOAD_SIZE |
| 51 | uses _ROMBASE |
| 52 | uses XIP_ROM_SIZE |
| 53 | uses XIP_ROM_BASE |
| 54 | uses STACK_SIZE |
| 55 | uses HEAP_SIZE |
| 56 | uses USE_OPTION_TABLE |
| 57 | uses LB_CKS_RANGE_START |
| 58 | uses LB_CKS_RANGE_END |
| 59 | uses LB_CKS_LOC |
| 60 | uses MAINBOARD_PART_NUMBER |
| 61 | uses MAINBOARD_VENDOR |
| 62 | uses MAINBOARD |
| 63 | uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID |
| 64 | uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID |
| 65 | uses COREBOOT_EXTRA_VERSION |
| 66 | uses _RAMBASE |
| 67 | uses TTYS0_BAUD |
| 68 | uses TTYS0_BASE |
| 69 | uses TTYS0_LCS |
| 70 | uses DEFAULT_CONSOLE_LOGLEVEL |
| 71 | uses MAXIMUM_CONSOLE_LOGLEVEL |
| 72 | uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 73 | uses CONFIG_CONSOLE_SERIAL8250 |
| 74 | uses HAVE_INIT_TIMER |
| 75 | uses CONFIG_GDB_STUB |
| 76 | uses CONFIG_GDB_STUB |
| 77 | uses CROSS_COMPILE |
| 78 | uses CC |
| 79 | uses HOSTCC |
| 80 | uses OBJCOPY |
| 81 | uses CONFIG_CHIP_NAME |
| 82 | uses CONFIG_CONSOLE_VGA |
| 83 | uses CONFIG_PCI_ROM_RUN |
| 84 | uses HW_MEM_HOLE_SIZEK |
| 85 | uses HW_MEM_HOLE_SIZE_AUTO_INC |
| 86 | uses K8_HT_FREQ_1G_SUPPORT |
| 87 | |
| 88 | uses HT_CHAIN_UNITID_BASE |
| 89 | uses HT_CHAIN_END_UNITID_BASE |
| 90 | uses SB_HT_CHAIN_ON_BUS0 |
| 91 | uses SB_HT_CHAIN_UNITID_OFFSET_ONLY |
| 92 | |
| 93 | uses USE_DCACHE_RAM |
| 94 | uses DCACHE_RAM_BASE |
| 95 | uses DCACHE_RAM_SIZE |
| 96 | uses DCACHE_RAM_GLOBAL_VAR_SIZE |
| 97 | uses CONFIG_USE_INIT |
| 98 | |
| 99 | uses SERIAL_CPU_INIT |
| 100 | |
| 101 | uses ENABLE_APIC_EXT_ID |
| 102 | uses APIC_ID_OFFSET |
| 103 | uses LIFT_BSP_APIC_ID |
| 104 | |
| 105 | uses CONFIG_PCI_64BIT_PREF_MEM |
| 106 | |
| 107 | uses CONFIG_LB_MEM_TOPK |
| 108 | |
| 109 | uses CONFIG_AP_CODE_IN_CAR |
| 110 | |
| 111 | uses MEM_TRAIN_SEQ |
| 112 | |
| 113 | uses WAIT_BEFORE_CPUS_INIT |
| 114 | |
| 115 | uses CONFIG_USE_PRINTK_IN_CAR |
| 116 | |
| 117 | ### |
| 118 | ### Build options |
| 119 | ### |
| 120 | |
| 121 | ## |
| 122 | ## ROM_SIZE is the size of boot ROM that this board will use. |
| 123 | ## |
| 124 | #default ROM_SIZE=524288 |
| 125 | default ROM_SIZE=0x100000 |
| 126 | |
| 127 | ## |
| 128 | ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use |
| 129 | ## |
| 130 | #default FALLBACK_SIZE=131072 |
| 131 | #default FALLBACK_SIZE=0x40000 |
| 132 | |
| 133 | #FALLBACK: 256K-4K |
| 134 | default FALLBACK_SIZE=0x3f000 |
| 135 | #FAILOVER: 4K |
| 136 | default FAILOVER_SIZE=0x01000 |
| 137 | |
| 138 | #more 1M for pgtbl |
| 139 | default CONFIG_LB_MEM_TOPK=2048 |
| 140 | |
| 141 | ## |
| 142 | ## Build code for the fallback boot |
| 143 | ## |
| 144 | default HAVE_FALLBACK_BOOT=1 |
| 145 | default HAVE_FAILOVER_BOOT=1 |
| 146 | |
| 147 | ## |
| 148 | ## Build code to reset the motherboard from coreboot |
| 149 | ## |
| 150 | default HAVE_HARD_RESET=1 |
| 151 | |
| 152 | ## |
| 153 | ## Build code to export a programmable irq routing table |
| 154 | ## |
| 155 | default HAVE_PIRQ_TABLE=1 |
| 156 | default IRQ_SLOT_COUNT=11 |
| 157 | |
| 158 | ## |
| 159 | ## Build code to export an x86 MP table |
| 160 | ## Useful for specifying IRQ routing values |
| 161 | ## |
| 162 | default HAVE_MP_TABLE=1 |
| 163 | |
| 164 | ## ACPI tables will be included |
| 165 | default HAVE_ACPI_TABLES=0 |
| 166 | |
| 167 | ## |
| 168 | ## Build code to export a CMOS option table |
| 169 | ## |
| 170 | default HAVE_OPTION_TABLE=1 |
| 171 | |
| 172 | ## |
| 173 | ## Move the default coreboot cmos range off of AMD RTC registers |
| 174 | ## |
| 175 | default LB_CKS_RANGE_START=49 |
| 176 | default LB_CKS_RANGE_END=122 |
| 177 | default LB_CKS_LOC=123 |
| 178 | |
| 179 | ## |
| 180 | ## Build code for SMP support |
| 181 | ## Only worry about 2 micro processors |
| 182 | ## |
| 183 | default CONFIG_SMP=1 |
| 184 | default CONFIG_MAX_CPUS=4 |
| 185 | default CONFIG_MAX_PHYSICAL_CPUS=2 |
| 186 | default CONFIG_LOGICAL_CPUS=1 |
| 187 | |
| 188 | default SERIAL_CPU_INIT=0 |
| 189 | |
| 190 | default ENABLE_APIC_EXT_ID=0 |
| 191 | default APIC_ID_OFFSET=0x10 |
| 192 | default LIFT_BSP_APIC_ID=1 |
| 193 | |
| 194 | #CHIP_NAME ? |
| 195 | default CONFIG_CHIP_NAME=1 |
| 196 | |
| 197 | #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. |
| 198 | #2G |
| 199 | #default HW_MEM_HOLE_SIZEK=0x200000 |
| 200 | #1G |
| 201 | default HW_MEM_HOLE_SIZEK=0x100000 |
| 202 | #512M |
| 203 | #default HW_MEM_HOLE_SIZEK=0x80000 |
| 204 | |
| 205 | #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy |
| 206 | #default HW_MEM_HOLE_SIZE_AUTO_INC=1 |
| 207 | |
| 208 | #Opteron K8 1G HT Support |
| 209 | default K8_HT_FREQ_1G_SUPPORT=1 |
| 210 | |
| 211 | #VGA Console |
| 212 | default CONFIG_CONSOLE_VGA=1 |
| 213 | default CONFIG_PCI_ROM_RUN=1 |
| 214 | |
| 215 | #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device |
| 216 | default HT_CHAIN_UNITID_BASE=0 |
| 217 | |
| 218 | #real SB Unit ID, default is 0x20, mean dont touch it at last |
| 219 | #default HT_CHAIN_END_UNITID_BASE=0x6 |
| 220 | |
| 221 | #make the SB HT chain on bus 0, default is not (0) |
| 222 | default SB_HT_CHAIN_ON_BUS0=2 |
| 223 | |
| 224 | #only offset for SB chain?, default is yes(1) |
| 225 | default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 |
| 226 | |
| 227 | #allow capable device use that above 4G |
| 228 | #default CONFIG_PCI_64BIT_PREF_MEM=1 |
| 229 | |
| 230 | ## |
| 231 | ## enable CACHE_AS_RAM specifics |
| 232 | ## |
| 233 | default USE_DCACHE_RAM=1 |
| 234 | default DCACHE_RAM_BASE=0xc8000 |
| 235 | default DCACHE_RAM_SIZE=0x08000 |
| 236 | default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 |
| 237 | default CONFIG_USE_INIT=0 |
| 238 | |
| 239 | default CONFIG_AP_CODE_IN_CAR=1 |
| 240 | default MEM_TRAIN_SEQ=1 |
| 241 | default WAIT_BEFORE_CPUS_INIT=1 |
| 242 | |
| 243 | ## |
| 244 | ## Build code to setup a generic IOAPIC |
| 245 | ## |
| 246 | default CONFIG_IOAPIC=1 |
| 247 | |
| 248 | ## |
| 249 | ## Clean up the motherboard id strings |
| 250 | ## |
| 251 | default MAINBOARD_PART_NUMBER="h8dmr" |
| 252 | default MAINBOARD_VENDOR="Supermicro" |
| 253 | default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 |
| 254 | default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 |
| 255 | |
| 256 | ### |
| 257 | ### coreboot layout values |
| 258 | ### |
| 259 | |
| 260 | ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. |
| 261 | default ROM_IMAGE_SIZE = 65536 |
| 262 | |
| 263 | ## |
| 264 | ## Use a small 8K stack |
| 265 | ## |
| 266 | default STACK_SIZE=0x2000 |
| 267 | |
| 268 | ## |
| 269 | ## Use a small 32K heap |
| 270 | ## |
| 271 | default HEAP_SIZE=0x8000 |
| 272 | |
| 273 | ## |
| 274 | ## Only use the option table in a normal image |
| 275 | ## |
| 276 | default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) |
| 277 | |
| 278 | ## |
| 279 | ## Coreboot C code runs at this location in RAM |
| 280 | ## |
| 281 | default _RAMBASE=0x00100000 |
| 282 | |
| 283 | ## |
| 284 | ## Load the payload from the ROM |
| 285 | ## |
| 286 | default CONFIG_ROM_PAYLOAD = 1 |
| 287 | |
| 288 | #default CONFIG_COMPRESSED_PAYLOAD = 1 |
| 289 | |
| 290 | ### |
| 291 | ### Defaults of options that you may want to override in the target config file |
| 292 | ### |
| 293 | |
| 294 | ## |
| 295 | ## The default compiler |
| 296 | ## |
| 297 | default CC="$(CROSS_COMPILE)gcc -m32" |
| 298 | default HOSTCC="gcc" |
| 299 | |
| 300 | ## |
| 301 | ## Disable the gdb stub by default |
| 302 | ## |
| 303 | default CONFIG_GDB_STUB=0 |
| 304 | |
| 305 | ## |
| 306 | ## The Serial Console |
| 307 | ## |
| 308 | default CONFIG_USE_PRINTK_IN_CAR=1 |
| 309 | |
| 310 | # To Enable the Serial Console |
| 311 | default CONFIG_CONSOLE_SERIAL8250=1 |
| 312 | |
| 313 | ## Select the serial console baud rate |
| 314 | default TTYS0_BAUD=115200 |
| 315 | #default TTYS0_BAUD=57600 |
| 316 | #default TTYS0_BAUD=38400 |
| 317 | #default TTYS0_BAUD=19200 |
| 318 | #default TTYS0_BAUD=9600 |
| 319 | #default TTYS0_BAUD=4800 |
| 320 | #default TTYS0_BAUD=2400 |
| 321 | #default TTYS0_BAUD=1200 |
| 322 | |
| 323 | # Select the serial console base port |
| 324 | default TTYS0_BASE=0x3f8 |
| 325 | |
| 326 | # Select the serial protocol |
| 327 | # This defaults to 8 data bits, 1 stop bit, and no parity |
| 328 | default TTYS0_LCS=0x3 |
| 329 | |
| 330 | ## |
| 331 | ### Select the coreboot loglevel |
| 332 | ## |
| 333 | ## EMERG 1 system is unusable |
| 334 | ## ALERT 2 action must be taken immediately |
| 335 | ## CRIT 3 critical conditions |
| 336 | ## ERR 4 error conditions |
| 337 | ## WARNING 5 warning conditions |
| 338 | ## NOTICE 6 normal but significant condition |
| 339 | ## INFO 7 informational |
| 340 | ## DEBUG 8 debug-level messages |
| 341 | ## SPEW 9 Way too many details |
| 342 | |
| 343 | ## Request this level of debugging output |
| 344 | default DEFAULT_CONSOLE_LOGLEVEL=9 |
| 345 | ## At a maximum only compile in this level of debugging |
| 346 | default MAXIMUM_CONSOLE_LOGLEVEL=9 |
| 347 | |
| 348 | ## |
| 349 | ## Select power on after power fail setting |
| 350 | default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" |
| 351 | |
| 352 | ### End Options.lb |
| 353 | end |