Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marshall Dawson | e7d892c | 2016-10-08 14:49:41 -0600 | [diff] [blame] | 4 | * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc. |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | * ROMSIG At ROMBASE + 0x20000: |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 18 | * 0 4 8 C |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 19 | * +------------+---------------+----------------+------------+ |
| 20 | * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | |
| 21 | * +------------+---------------+----------------+------------+ |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 22 | * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either |
| 23 | * +------------+---------------+ 2nd PSP directory or PSP COMBO directory |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 24 | * EC ROM should be 64K aligned. |
| 25 | * |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 26 | * PSP directory (Where "PSPDIR ADDR" points) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 27 | * +------------+---------------+----------------+------------+ |
| 28 | * | 'PSP$' | Fletcher | Count | Reserved | |
| 29 | * +------------+---------------+----------------+------------+ |
| 30 | * | 0 | size | Base address | Reserved | Pubkey |
| 31 | * +------------+---------------+----------------+------------+ |
| 32 | * | 1 | size | Base address | Reserved | Bootloader |
| 33 | * +------------+---------------+----------------+------------+ |
| 34 | * | 8 | size | Base address | Reserved | Smu Firmware |
| 35 | * +------------+---------------+----------------+------------+ |
| 36 | * | 3 | size | Base address | Reserved | Recovery Firmware |
| 37 | * +------------+---------------+----------------+------------+ |
| 38 | * | | |
| 39 | * | | |
| 40 | * | Other PSP Firmware | |
| 41 | * | | |
| 42 | * | | |
| 43 | * +------------+---------------+----------------+------------+ |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 44 | * |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 45 | * PSP Combo directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 46 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 47 | * | 'PSP2' | Fletcher | Count |Look up mode| |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 48 | * +------------+---------------+----------------+------------+ |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 49 | * | R e s e r v e d | |
| 50 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 51 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 52 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 53 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 54 | * +------------+---------------+----------------+------------+ |
| 55 | * | | |
| 56 | * | Other PSP | |
| 57 | * | | |
| 58 | * +------------+---------------+----------------+------------+ |
| 59 | * |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 60 | */ |
| 61 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 62 | #include <fcntl.h> |
| 63 | #include <errno.h> |
| 64 | #include <stdio.h> |
| 65 | #include <sys/stat.h> |
| 66 | #include <sys/types.h> |
| 67 | #include <unistd.h> |
| 68 | #include <string.h> |
| 69 | #include <stdlib.h> |
| 70 | #include <getopt.h> |
| 71 | |
| 72 | #ifndef CONFIG_ROM_SIZE |
| 73 | #define CONFIG_ROM_SIZE 0x400000 |
| 74 | #endif |
| 75 | |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 76 | #define AMD_ROMSIG_OFFSET 0x20000 |
| 77 | #define MIN_ROM_KB 256 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 78 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 79 | #define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1)) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 80 | #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) |
| 81 | #define ERASE_ALIGNMENT 0x1000U |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 82 | #define TABLE_ALIGNMENT 0x1000U |
| 83 | #define BLOB_ALIGNMENT 0x100U |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 84 | #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 85 | #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 86 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 87 | #define DEFAULT_SOFT_FUSE_CHAIN "0x1" |
| 88 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 89 | #define EMBEDDED_FW_SIGNATURE 0x55aa55aa |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 90 | #define PSP_COOKIE 0x50535024 /* 'PSP$' */ |
| 91 | #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ |
| 92 | #define PSP2_COOKIE 0x50535032 /* 'PSP2' */ |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 93 | #define BDT1_COOKIE 0x44484224 /* 'DHB$ */ |
| 94 | #define BDT2_COOKIE 0x324c4224 /* '2LB$ */ |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 95 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 96 | /* |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 97 | * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP |
| 98 | * can support an optional "combo" implementation. If the PSP sees the |
| 99 | * PSP2 cookie, it interprets the table as a roadmap to additional PSP |
| 100 | * tables. Using this, support for multiple product generations may be |
| 101 | * built into one image. If the PSP$ cookie is found, the table is a |
| 102 | * normal directory table. |
| 103 | * |
| 104 | * Modern generations supporting the combo directories require the |
| 105 | * pointer to be at offset 0x14 of the Embedded Firmware Structure, |
| 106 | * regardless of the type of directory used. The --combo-capable |
| 107 | * argument enforces this placement. |
| 108 | * |
| 109 | * TODO: Future work may require fully implementing the PSP_COMBO feature. |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 110 | */ |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 111 | #define PSP_COMBO 0 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 112 | |
Idwer Vollering | a682fc8 | 2019-12-16 15:33:12 +0100 | [diff] [blame] | 113 | #if defined(__GLIBC__) |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 114 | typedef unsigned long long int uint64_t; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 115 | typedef unsigned int uint32_t; |
| 116 | typedef unsigned char uint8_t; |
| 117 | typedef unsigned short uint16_t; |
Idwer Vollering | a682fc8 | 2019-12-16 15:33:12 +0100 | [diff] [blame] | 118 | #endif |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. |
| 122 | * The checksum field of the passed PDU does not need to be reset to zero. |
| 123 | * |
| 124 | * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of |
| 125 | * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an |
| 126 | * alternative to cyclical redundancy checks because it provides error- |
| 127 | * detection properties similar to cyclical redundancy checks but at the |
| 128 | * cost of a simple summation technique. Its characteristics were first |
| 129 | * published in IEEE Transactions on Communications in January 1982. One |
| 130 | * version has been adopted by ISO for use in the class-4 transport layer |
| 131 | * of the network protocol. |
| 132 | * |
| 133 | * This program expects: |
| 134 | * stdin: The input file to compute a checksum for. The input file |
| 135 | * not be longer than 256 bytes. |
| 136 | * stdout: Copied from the input file with the Fletcher's Checksum |
| 137 | * inserted 8 bytes after the beginning of the file. |
| 138 | * stderr: Used to print out error messages. |
| 139 | */ |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 140 | static uint32_t fletcher32(const void *data, int length) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 141 | { |
| 142 | uint32_t c0; |
| 143 | uint32_t c1; |
| 144 | uint32_t checksum; |
| 145 | int index; |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 146 | const uint16_t *pptr = data; |
| 147 | |
| 148 | length /= 2; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 149 | |
| 150 | c0 = 0xFFFF; |
| 151 | c1 = 0xFFFF; |
| 152 | |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 153 | while (length) { |
| 154 | index = length >= 359 ? 359 : length; |
| 155 | length -= index; |
| 156 | do { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 157 | c0 += *(pptr++); |
| 158 | c1 += c0; |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 159 | } while (--index); |
| 160 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 161 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 162 | } |
| 163 | |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 164 | /* Sums[0,1] mod 64K + overflow */ |
| 165 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 166 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 167 | checksum = (c1 << 16) | c0; |
| 168 | |
| 169 | return checksum; |
| 170 | } |
| 171 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 172 | static void usage(void) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 173 | { |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 174 | printf("amdfwtool: Create AMD Firmware combination\n"); |
| 175 | printf("Usage: amdfwtool [options] -f <size> -o <filename>\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 176 | printf("-x | --xhci <FILE> Add XHCI blob\n"); |
| 177 | printf("-i | --imc <FILE> Add IMC blob\n"); |
| 178 | printf("-g | --gec <FILE> Add GEC blob\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 179 | |
| 180 | printf("\nPSP options:\n"); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 181 | printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n"); |
| 182 | printf(" offset able to support combo directory\n"); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 183 | printf("-M | --multilevel Generate primary and secondary tables\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 184 | printf("-p | --pubkey <FILE> Add pubkey\n"); |
| 185 | printf("-b | --bootloader <FILE> Add bootloader\n"); |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 186 | printf("-S | --subprogram <number> Sets subprogram field for the next firmware\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 187 | printf("-s | --smufirmware <FILE> Add smufirmware\n"); |
| 188 | printf("-r | --recovery <FILE> Add recovery\n"); |
| 189 | printf("-k | --rtmpubkey <FILE> Add rtmpubkey\n"); |
| 190 | printf("-c | --secureos <FILE> Add secureos\n"); |
| 191 | printf("-n | --nvram <FILE> Add nvram\n"); |
| 192 | printf("-d | --securedebug <FILE> Add securedebug\n"); |
| 193 | printf("-t | --trustlets <FILE> Add trustlets\n"); |
| 194 | printf("-u | --trustletkey <FILE> Add trustletkey\n"); |
| 195 | printf("-w | --smufirmware2 <FILE> Add smufirmware2\n"); |
| 196 | printf("-m | --smuscs <FILE> Add smuscs\n"); |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 197 | printf("-T | --soft-fuse <HEX_VAL> Override default soft fuse values\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 198 | printf("-z | --abl-image <FILE> Add AGESA Binary\n"); |
| 199 | printf("-J | --sec-gasket <FILE> Add security gasket\n"); |
| 200 | printf("-B | --mp2-fw <FILE> Add MP2 firmware\n"); |
| 201 | printf("-N | --secdebug <FILE> Add secure unlock image\n"); |
| 202 | printf("-U | --token-unlock Reserve space for debug token\n"); |
| 203 | printf("-K | --drv-entry-pts <FILE> Add PSP driver entry points\n"); |
| 204 | printf("-L | --ikek <FILE> Add Wrapped iKEK\n"); |
| 205 | printf("-Y | --s0i3drv <FILE> Add s0i3 driver\n"); |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 206 | printf("-Z | --verstage <FILE> Add verstage\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 207 | printf("\nBIOS options:\n"); |
| 208 | printf("-I | --instance <number> Sets instance field for the next BIOS firmware\n"); |
| 209 | printf("-a | --apcb <FILE> Add AGESA PSP customization block\n"); |
| 210 | printf("-Q | --apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); |
| 211 | printf("-F | --apob-nv-base <HEX_VAL> Location of S3 resume data\n"); |
| 212 | printf("-H | --apob-nv-size <HEX_VAL> Size of S3 resume data\n"); |
| 213 | printf("-y | --pmu-inst <FILE> Add PMU firmware instruction portion\n"); |
| 214 | printf("-G | --pmu-data <FILE> Add PMU firmware data portion\n"); |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 215 | printf("-O | --ucode <FILE> Add microcode patch\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 216 | printf("-X | --mp2-config <FILE> Add MP2 configuration\n"); |
| 217 | printf("-V | --bios-bin <FILE> Add compressed image; auto source address\n"); |
| 218 | printf("-e | --bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); |
| 219 | printf("-v | --bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); |
| 220 | printf("-j | --bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 221 | printf("\n-o | --output <filename> output filename\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 222 | printf("-f | --flashsize <HEX_VAL> ROM size in bytes\n"); |
| 223 | printf(" size must be larger than %dKB\n", |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 224 | MIN_ROM_KB); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 225 | printf(" and must a multiple of 1024\n"); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 226 | printf("-l | --location Location of Directory\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 227 | printf("-h | --help show this help\n"); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 228 | } |
| 229 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 230 | typedef enum _amd_bios_type { |
| 231 | AMD_BIOS_APCB = 0x60, |
| 232 | AMD_BIOS_APOB = 0x61, |
| 233 | AMD_BIOS_BIN = 0x62, |
| 234 | AMD_BIOS_APOB_NV = 0x63, |
| 235 | AMD_BIOS_PMUI = 0x64, |
| 236 | AMD_BIOS_PMUD = 0x65, |
| 237 | AMD_BIOS_UCODE = 0x66, |
| 238 | AMD_BIOS_APCB_BK = 0x68, |
| 239 | AMD_BIOS_MP2_CFG = 0x6a, |
| 240 | AMD_BIOS_L2_PTR = 0x70, |
| 241 | AMD_BIOS_INVALID, |
| 242 | } amd_bios_type; |
| 243 | |
| 244 | #define BDT_LVL1 0x1 |
| 245 | #define BDT_LVL2 0x2 |
| 246 | #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) |
| 247 | typedef struct _amd_bios_entry { |
| 248 | amd_bios_type type; |
| 249 | int region_type; |
| 250 | int reset; |
| 251 | int copy; |
| 252 | int ro; |
| 253 | int zlib; |
| 254 | int inst; |
| 255 | int subpr; |
| 256 | uint64_t src; |
| 257 | uint64_t dest; |
| 258 | size_t size; |
| 259 | char *filename; |
| 260 | int level; |
| 261 | } amd_bios_entry; |
| 262 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 263 | typedef enum _amd_fw_type { |
| 264 | AMD_FW_PSP_PUBKEY = 0, |
| 265 | AMD_FW_PSP_BOOTLOADER = 1, |
| 266 | AMD_FW_PSP_SMU_FIRMWARE = 8, |
| 267 | AMD_FW_PSP_RECOVERY = 3, |
| 268 | AMD_FW_PSP_RTM_PUBKEY = 5, |
| 269 | AMD_FW_PSP_SECURED_OS = 2, |
| 270 | AMD_FW_PSP_NVRAM = 4, |
| 271 | AMD_FW_PSP_SECURED_DEBUG = 9, |
| 272 | AMD_FW_PSP_TRUSTLETS = 12, |
| 273 | AMD_FW_PSP_TRUSTLETKEY = 13, |
| 274 | AMD_FW_PSP_SMU_FIRMWARE2 = 18, |
| 275 | AMD_PSP_FUSE_CHAIN = 11, |
| 276 | AMD_FW_PSP_SMUSCS = 95, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 277 | AMD_DEBUG_UNLOCK = 0x13, |
| 278 | AMD_WRAPPED_IKEK = 0x21, |
| 279 | AMD_TOKEN_UNLOCK = 0x22, |
| 280 | AMD_SEC_GASKET = 0x24, |
| 281 | AMD_MP2_FW = 0x25, |
| 282 | AMD_DRIVER_ENTRIES = 0x28, |
| 283 | AMD_S0I3_DRIVER = 0x2d, |
| 284 | AMD_ABL0 = 0x30, |
| 285 | AMD_ABL1 = 0x31, |
| 286 | AMD_ABL2 = 0x32, |
| 287 | AMD_ABL3 = 0x33, |
| 288 | AMD_ABL4 = 0x34, |
| 289 | AMD_ABL5 = 0x35, |
| 290 | AMD_ABL6 = 0x36, |
| 291 | AMD_ABL7 = 0x37, |
| 292 | AMD_FW_PSP_WHITELIST = 0x3a, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 293 | AMD_FW_L2_PTR = 0x40, |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 294 | AMD_FW_PSP_VERSTAGE = 0x52, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 295 | AMD_FW_IMC, |
| 296 | AMD_FW_GEC, |
| 297 | AMD_FW_XHCI, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 298 | AMD_FW_INVALID, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 299 | } amd_fw_type; |
| 300 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 301 | #define PSP_LVL1 0x1 |
| 302 | #define PSP_LVL2 0x2 |
| 303 | #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 304 | typedef struct _amd_fw_entry { |
| 305 | amd_fw_type type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 306 | uint8_t subprog; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 307 | char *filename; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 308 | int level; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 309 | uint64_t other; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 310 | } amd_fw_entry; |
| 311 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 312 | static amd_fw_entry amd_psp_fw_table[] = { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 313 | { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, |
| 314 | { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, |
| 315 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, |
| 316 | { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, |
| 317 | { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, |
| 318 | { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, |
| 319 | { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, |
| 320 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, |
| 321 | { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, |
| 322 | { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, |
| 323 | { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, |
| 324 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, |
| 325 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, |
| 326 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, |
| 327 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, |
| 328 | { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, |
| 329 | { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 330 | { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, |
| 331 | { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, |
| 332 | { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH }, |
| 333 | { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, |
| 334 | { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, |
| 335 | { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, |
| 336 | { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, |
| 337 | { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, |
| 338 | { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, |
| 339 | { .type = AMD_ABL0, .level = PSP_BOTH }, |
| 340 | { .type = AMD_ABL1, .level = PSP_BOTH }, |
| 341 | { .type = AMD_ABL2, .level = PSP_BOTH }, |
| 342 | { .type = AMD_ABL3, .level = PSP_BOTH }, |
| 343 | { .type = AMD_ABL4, .level = PSP_BOTH }, |
| 344 | { .type = AMD_ABL5, .level = PSP_BOTH }, |
| 345 | { .type = AMD_ABL6, .level = PSP_BOTH }, |
| 346 | { .type = AMD_ABL7, .level = PSP_BOTH }, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 347 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, |
| 348 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 349 | { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 350 | { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 351 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 352 | }; |
| 353 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 354 | static amd_fw_entry amd_fw_table[] = { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 355 | { .type = AMD_FW_XHCI }, |
| 356 | { .type = AMD_FW_IMC }, |
| 357 | { .type = AMD_FW_GEC }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 358 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 359 | }; |
| 360 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 361 | static amd_bios_entry amd_bios_table[] = { |
Marshall Dawson | 0581bf6 | 2019-09-25 11:03:53 -0600 | [diff] [blame] | 362 | { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, |
| 363 | { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, |
| 364 | { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, |
| 365 | { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, |
| 366 | { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 367 | { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, |
| 368 | { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, |
| 369 | { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, |
| 370 | { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, |
| 371 | { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, |
| 372 | { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, |
| 373 | { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, |
| 374 | { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, |
| 375 | { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, |
| 376 | { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, |
| 377 | { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | 2dd3b5c | 2020-01-03 17:57:48 -0700 | [diff] [blame] | 378 | { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, |
| 379 | { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, |
| 380 | { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, |
| 381 | { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, |
| 382 | { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 383 | { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, |
| 384 | { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, |
| 385 | { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, |
| 386 | { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, |
| 387 | { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, |
| 388 | { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, |
| 389 | { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, |
| 390 | { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, |
| 391 | { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, |
| 392 | { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, |
| 393 | { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 394 | { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, |
| 395 | { .type = AMD_BIOS_BIN, |
| 396 | .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, |
| 397 | { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, |
| 398 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 399 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 400 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 401 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 402 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 403 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 404 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 405 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 406 | { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, |
| 407 | { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, |
| 408 | { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |
| 409 | { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, |
| 410 | { .type = AMD_BIOS_INVALID }, |
| 411 | }; |
| 412 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 413 | typedef struct _embedded_firmware { |
| 414 | uint32_t signature; /* 0x55aa55aa */ |
| 415 | uint32_t imc_entry; |
| 416 | uint32_t gec_entry; |
| 417 | uint32_t xhci_entry; |
| 418 | uint32_t psp_entry; |
| 419 | uint32_t comboable; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 420 | uint32_t bios0_entry; /* todo: add way to select correct entry */ |
| 421 | uint32_t bios1_entry; |
Marshall Dawson | 94f2492 | 2019-09-28 08:49:09 -0600 | [diff] [blame] | 422 | uint32_t bios2_entry; |
| 423 | uint32_t reserved[0x2c]; /* 0x24 - 0x4f */ |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 424 | } __attribute__((packed, aligned(16))) embedded_firmware; |
| 425 | |
| 426 | typedef struct _psp_directory_header { |
| 427 | uint32_t cookie; |
| 428 | uint32_t checksum; |
| 429 | uint32_t num_entries; |
| 430 | uint32_t reserved; |
| 431 | } __attribute__((packed, aligned(16))) psp_directory_header; |
| 432 | |
| 433 | typedef struct _psp_directory_entry { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 434 | uint8_t type; |
| 435 | uint8_t subprog; |
| 436 | uint16_t rsvd; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 437 | uint32_t size; |
| 438 | uint64_t addr; /* or a value in some cases */ |
| 439 | } __attribute__((packed)) psp_directory_entry; |
| 440 | |
| 441 | typedef struct _psp_directory_table { |
| 442 | psp_directory_header header; |
| 443 | psp_directory_entry entries[]; |
| 444 | } __attribute__((packed)) psp_directory_table; |
| 445 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 446 | #define MAX_PSP_ENTRIES 0x1f |
| 447 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 448 | typedef struct _psp_combo_header { |
| 449 | uint32_t cookie; |
| 450 | uint32_t checksum; |
| 451 | uint32_t num_entries; |
| 452 | uint32_t lookup; |
| 453 | uint64_t reserved[2]; |
| 454 | } __attribute__((packed, aligned(16))) psp_combo_header; |
| 455 | |
| 456 | typedef struct _psp_combo_entry { |
| 457 | uint32_t id_sel; |
| 458 | uint32_t id; |
| 459 | uint64_t lvl2_addr; |
| 460 | } __attribute__((packed)) psp_combo_entry; |
| 461 | |
| 462 | typedef struct _psp_combo_directory { |
| 463 | psp_combo_header header; |
| 464 | psp_combo_entry entries[]; |
| 465 | } __attribute__((packed)) psp_combo_directory; |
| 466 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 467 | #define MAX_COMBO_ENTRIES 1 |
| 468 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 469 | typedef struct _bios_directory_hdr { |
| 470 | uint32_t cookie; |
| 471 | uint32_t checksum; |
| 472 | uint32_t num_entries; |
| 473 | uint32_t reserved; |
| 474 | } __attribute__((packed, aligned(16))) bios_directory_hdr; |
| 475 | |
| 476 | typedef struct _bios_directory_entry { |
| 477 | uint8_t type; |
| 478 | uint8_t region_type; |
| 479 | int reset:1; |
| 480 | int copy:1; |
| 481 | int ro:1; |
| 482 | int compressed:1; |
| 483 | int inst:4; |
| 484 | uint8_t subprog; /* b[7:3] reserved */ |
| 485 | uint32_t size; |
| 486 | uint64_t source; |
| 487 | uint64_t dest; |
| 488 | } __attribute__((packed)) bios_directory_entry; |
| 489 | |
| 490 | typedef struct _bios_directory_table { |
| 491 | bios_directory_hdr header; |
| 492 | bios_directory_entry entries[]; |
| 493 | } bios_directory_table; |
| 494 | |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 495 | #define MAX_BIOS_ENTRIES 0x22 |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 496 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 497 | typedef struct _context { |
| 498 | char *rom; /* target buffer, size of flash device */ |
| 499 | uint32_t rom_size; /* size of flash device */ |
| 500 | uint32_t current; /* pointer within flash & proxy buffer */ |
| 501 | } context; |
| 502 | |
| 503 | #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) |
| 504 | #define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) |
| 505 | #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) |
| 506 | #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) |
| 507 | #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) |
| 508 | #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) |
| 509 | #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) |
| 510 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 511 | static void *new_psp_dir(context *ctx, int multi) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 512 | { |
| 513 | void *ptr; |
| 514 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 515 | /* |
| 516 | * Force both onto boundary when multi. Primary table is after |
| 517 | * updatable table, so alignment ensures primary can stay intact |
| 518 | * if secondary is reprogrammed. |
| 519 | */ |
| 520 | if (multi) |
| 521 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 522 | else |
| 523 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 524 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 525 | ptr = BUFF_CURRENT(*ctx); |
| 526 | ctx->current += sizeof(psp_directory_header) |
| 527 | + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); |
| 528 | return ptr; |
| 529 | } |
| 530 | |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 531 | #if PSP_COMBO |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 532 | static void *new_combo_dir(context *ctx) |
| 533 | { |
| 534 | void *ptr; |
| 535 | |
| 536 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 537 | ptr = BUFF_CURRENT(*ctx); |
| 538 | ctx->current += sizeof(psp_combo_header) |
| 539 | + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry); |
| 540 | return ptr; |
| 541 | } |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 542 | #endif |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 543 | |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 544 | static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 545 | { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 546 | psp_combo_directory *cdir = directory; |
| 547 | psp_directory_table *dir = directory; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 548 | bios_directory_table *bdir = directory; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 549 | |
| 550 | if (!count) |
| 551 | return; |
| 552 | |
| 553 | switch (cookie) { |
| 554 | case PSP2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 555 | /* caller is responsible for lookup mode */ |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 556 | cdir->header.cookie = cookie; |
| 557 | cdir->header.num_entries = count; |
| 558 | cdir->header.reserved[0] = 0; |
| 559 | cdir->header.reserved[1] = 0; |
| 560 | /* checksum everything that comes after the Checksum field */ |
| 561 | cdir->header.checksum = fletcher32(&cdir->header.num_entries, |
| 562 | count * sizeof(psp_combo_entry) |
| 563 | + sizeof(cdir->header.num_entries) |
| 564 | + sizeof(cdir->header.lookup) |
| 565 | + 2 * sizeof(cdir->header.reserved[0])); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 566 | break; |
| 567 | case PSP_COOKIE: |
| 568 | case PSPL2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 569 | dir->header.cookie = cookie; |
| 570 | dir->header.num_entries = count; |
| 571 | dir->header.reserved = 0; |
| 572 | /* checksum everything that comes after the Checksum field */ |
| 573 | dir->header.checksum = fletcher32(&dir->header.num_entries, |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 574 | count * sizeof(psp_directory_entry) |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 575 | + sizeof(dir->header.num_entries) |
| 576 | + sizeof(dir->header.reserved)); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 577 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 578 | case BDT1_COOKIE: |
| 579 | case BDT2_COOKIE: |
| 580 | bdir->header.cookie = cookie; |
| 581 | bdir->header.num_entries = count; |
| 582 | bdir->header.reserved = 0; |
| 583 | /* checksum everything that comes after the Checksum field */ |
| 584 | bdir->header.checksum = fletcher32(&bdir->header.num_entries, |
| 585 | count * sizeof(bios_directory_entry) |
| 586 | + sizeof(bdir->header.num_entries) |
| 587 | + sizeof(bdir->header.reserved)); |
| 588 | break; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 589 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 590 | } |
| 591 | |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 592 | static ssize_t copy_blob(void *dest, const char *src_file, size_t room) |
| 593 | { |
| 594 | int fd; |
| 595 | struct stat fd_stat; |
| 596 | ssize_t bytes; |
| 597 | |
| 598 | fd = open(src_file, O_RDONLY); |
| 599 | if (fd < 0) { |
Eric Peers | af50567 | 2020-03-05 16:04:15 -0700 | [diff] [blame] | 600 | printf("Error opening file: %s: %s\n", |
| 601 | src_file, strerror(errno)); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 602 | return -1; |
| 603 | } |
| 604 | |
| 605 | if (fstat(fd, &fd_stat)) { |
| 606 | printf("fstat error: %s\n", strerror(errno)); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 607 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 608 | return -2; |
| 609 | } |
| 610 | |
| 611 | if (fd_stat.st_size > room) { |
| 612 | printf("Error: %s will not fit. Exiting.\n", src_file); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 613 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 614 | return -3; |
| 615 | } |
| 616 | |
| 617 | bytes = read(fd, dest, (size_t)fd_stat.st_size); |
| 618 | close(fd); |
| 619 | if (bytes != (ssize_t)fd_stat.st_size) { |
| 620 | printf("Error while reading %s\n", src_file); |
| 621 | return -4; |
| 622 | } |
| 623 | |
| 624 | return bytes; |
| 625 | } |
| 626 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 627 | static void integrate_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 628 | embedded_firmware *romsig, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 629 | amd_fw_entry *fw_table) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 630 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 631 | ssize_t bytes; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 632 | int i; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 633 | |
| 634 | ctx->current += sizeof(embedded_firmware); |
| 635 | ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 636 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 637 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 638 | if (fw_table[i].filename != NULL) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 639 | switch (fw_table[i].type) { |
| 640 | case AMD_FW_IMC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 641 | ctx->current = ALIGN(ctx->current, 0x10000U); |
| 642 | romsig->imc_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 643 | break; |
| 644 | case AMD_FW_GEC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 645 | romsig->gec_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 646 | break; |
| 647 | case AMD_FW_XHCI: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 648 | romsig->xhci_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 649 | break; |
| 650 | default: |
| 651 | /* Error */ |
| 652 | break; |
| 653 | } |
| 654 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 655 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 656 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 657 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 658 | free(ctx->rom); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 659 | exit(1); |
| 660 | } |
| 661 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 662 | ctx->current = ALIGN(ctx->current + bytes, |
| 663 | BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 664 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 665 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 666 | } |
| 667 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 668 | static void integrate_psp_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 669 | psp_directory_table *pspdir, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 670 | psp_directory_table *pspdir2, |
| 671 | amd_fw_entry *fw_table, |
| 672 | uint32_t cookie) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 673 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 674 | ssize_t bytes; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 675 | unsigned int i, count; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 676 | int level; |
| 677 | |
| 678 | /* This function can create a primary table, a secondary table, or a |
| 679 | * flattened table which contains all applicable types. These if-else |
| 680 | * statements infer what the caller intended. If a 2nd-level cookie |
| 681 | * is passed, clearly a 2nd-level table is intended. However, a |
| 682 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 683 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 684 | */ |
| 685 | if (cookie == PSPL2_COOKIE) |
| 686 | level = PSP_LVL2; |
| 687 | else if (pspdir2) |
| 688 | level = PSP_LVL1; |
| 689 | else |
| 690 | level = PSP_BOTH; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 691 | |
| 692 | ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 693 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 694 | for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 695 | if (!(fw_table[i].level & level)) |
| 696 | continue; |
| 697 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 698 | if (fw_table[i].type == AMD_TOKEN_UNLOCK) { |
| 699 | if (!fw_table[i].other) |
| 700 | continue; |
| 701 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 702 | pspdir->entries[count].type = fw_table[i].type; |
| 703 | pspdir->entries[count].size = 4096; /* TODO: doc? */ |
| 704 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 705 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 706 | pspdir->entries[count].rsvd = 0; |
| 707 | ctx->current = ALIGN(ctx->current + 4096, 0x100U); |
| 708 | count++; |
| 709 | } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 710 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 711 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 712 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 713 | pspdir->entries[count].size = 0xFFFFFFFF; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 714 | pspdir->entries[count].addr = fw_table[i].other; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 715 | count++; |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 716 | } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { |
| 717 | if (fw_table[i].filename == NULL) |
| 718 | continue; |
| 719 | /* TODO: Add a way to reserve for NVRAM without |
| 720 | * requiring a filename. This isn't a feature used |
| 721 | * by coreboot systems, so priority is very low. |
| 722 | */ |
| 723 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 724 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 725 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 726 | if (bytes <= 0) { |
| 727 | free(ctx->rom); |
| 728 | exit(1); |
| 729 | } |
| 730 | |
| 731 | pspdir->entries[count].type = fw_table[i].type; |
| 732 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 733 | pspdir->entries[count].rsvd = 0; |
| 734 | pspdir->entries[count].size = ALIGN(bytes, |
| 735 | ERASE_ALIGNMENT); |
| 736 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 737 | |
| 738 | ctx->current = ALIGN(ctx->current + bytes, |
| 739 | BLOB_ERASE_ALIGNMENT); |
| 740 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 741 | } else if (fw_table[i].filename != NULL) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 742 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 743 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 744 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 745 | free(ctx->rom); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 746 | exit(1); |
| 747 | } |
| 748 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 749 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 750 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 751 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 752 | pspdir->entries[count].size = (uint32_t)bytes; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 753 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 754 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 755 | ctx->current = ALIGN(ctx->current + bytes, |
| 756 | BLOB_ALIGNMENT); |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 757 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 758 | } else { |
| 759 | /* This APU doesn't have this firmware. */ |
| 760 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 761 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 762 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 763 | if (pspdir2) { |
| 764 | pspdir->entries[count].type = AMD_FW_L2_PTR; |
| 765 | pspdir->entries[count].subprog = 0; |
| 766 | pspdir->entries[count].rsvd = 0; |
| 767 | pspdir->entries[count].size = sizeof(pspdir2->header) |
| 768 | + pspdir2->header.num_entries |
| 769 | * sizeof(psp_directory_entry); |
| 770 | |
| 771 | pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2); |
| 772 | count++; |
| 773 | } |
| 774 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 775 | if (count > MAX_PSP_ENTRIES) { |
| 776 | printf("Error: PSP entries exceed max allowed items\n"); |
| 777 | free(ctx->rom); |
| 778 | exit(1); |
| 779 | } |
| 780 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 781 | fill_dir_header(pspdir, count, cookie); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 782 | } |
| 783 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 784 | static void *new_bios_dir(context *ctx, int multi) |
| 785 | { |
| 786 | void *ptr; |
| 787 | |
| 788 | /* |
| 789 | * Force both onto boundary when multi. Primary table is after |
| 790 | * updatable table, so alignment ensures primary can stay intact |
| 791 | * if secondary is reprogrammed. |
| 792 | */ |
| 793 | if (multi) |
| 794 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 795 | else |
| 796 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 797 | ptr = BUFF_CURRENT(*ctx); |
| 798 | ctx->current += sizeof(bios_directory_hdr) |
| 799 | + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); |
| 800 | return ptr; |
| 801 | } |
| 802 | |
| 803 | static int locate_bdt2_bios(bios_directory_table *level2, |
| 804 | uint64_t *source, uint32_t *size) |
| 805 | { |
| 806 | int i; |
| 807 | |
| 808 | *source = 0; |
| 809 | *size = 0; |
| 810 | if (!level2) |
| 811 | return 0; |
| 812 | |
| 813 | for (i = 0 ; i < level2->header.num_entries ; i++) { |
| 814 | if (level2->entries[i].type == AMD_BIOS_BIN) { |
| 815 | *source = level2->entries[i].source; |
| 816 | *size = level2->entries[i].size; |
| 817 | return 1; |
| 818 | } |
| 819 | } |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | static int have_bios_tables(amd_bios_entry *table) |
| 824 | { |
| 825 | int i; |
| 826 | |
| 827 | for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) { |
| 828 | if (table[i].level & BDT_LVL1 && table[i].filename) |
| 829 | return 1; |
| 830 | } |
| 831 | return 0; |
| 832 | } |
| 833 | |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 834 | static int find_bios_entry(amd_bios_type type) |
| 835 | { |
| 836 | int i; |
| 837 | |
| 838 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 839 | if (amd_bios_table[i].type == type) |
| 840 | return i; |
| 841 | } |
| 842 | return -1; |
| 843 | } |
| 844 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 845 | static void integrate_bios_firmwares(context *ctx, |
| 846 | bios_directory_table *biosdir, |
| 847 | bios_directory_table *biosdir2, |
| 848 | amd_bios_entry *fw_table, |
| 849 | uint32_t cookie) |
| 850 | { |
| 851 | ssize_t bytes; |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 852 | unsigned int i, count; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 853 | int level; |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 854 | int apob_idx; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 855 | |
| 856 | /* This function can create a primary table, a secondary table, or a |
| 857 | * flattened table which contains all applicable types. These if-else |
| 858 | * statements infer what the caller intended. If a 2nd-level cookie |
| 859 | * is passed, clearly a 2nd-level table is intended. However, a |
| 860 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 861 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 862 | */ |
| 863 | if (cookie == BDT2_COOKIE) |
| 864 | level = BDT_LVL2; |
| 865 | else if (biosdir2) |
| 866 | level = BDT_LVL1; |
| 867 | else |
| 868 | level = BDT_BOTH; |
| 869 | |
| 870 | ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); |
| 871 | |
| 872 | for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { |
| 873 | if (!(fw_table[i].level & level)) |
| 874 | continue; |
| 875 | if (fw_table[i].filename == NULL && ( |
| 876 | fw_table[i].type != AMD_BIOS_APOB && |
| 877 | fw_table[i].type != AMD_BIOS_APOB_NV && |
| 878 | fw_table[i].type != AMD_BIOS_L2_PTR && |
| 879 | fw_table[i].type != AMD_BIOS_BIN)) |
| 880 | continue; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 881 | |
| 882 | /* BIOS Directory items may have additional requirements */ |
| 883 | |
| 884 | /* APOB_NV must have a size if it has a source */ |
| 885 | if (fw_table[i].type == AMD_BIOS_APOB_NV && fw_table[i].src) { |
| 886 | if (!fw_table[i].size) { |
| 887 | printf("Error: APOB NV address provided, but no size\n"); |
| 888 | free(ctx->rom); |
| 889 | exit(1); |
| 890 | } |
| 891 | } |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 892 | /* APOB_NV needs a size, else no choice but to skip the item */ |
| 893 | if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) { |
| 894 | /* Attempt to determine whether this is an error */ |
| 895 | apob_idx = find_bios_entry(AMD_BIOS_APOB); |
| 896 | if (apob_idx < 0 || !fw_table[apob_idx].dest) { |
| 897 | /* APOV NV not expected to be used */ |
| 898 | continue; |
| 899 | } else { |
| 900 | printf("Error: APOB NV must have a size\n"); |
| 901 | free(ctx->rom); |
| 902 | exit(1); |
| 903 | } |
| 904 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 905 | |
| 906 | /* APOB_DATA needs destination */ |
| 907 | if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { |
| 908 | printf("Error: APOB destination not provided\n"); |
| 909 | free(ctx->rom); |
| 910 | exit(1); |
| 911 | } |
| 912 | |
| 913 | /* BIOS binary must have destination and uncompressed size. If |
| 914 | * no filename given, then user must provide a source address. |
| 915 | */ |
| 916 | if (fw_table[i].type == AMD_BIOS_BIN) { |
| 917 | if (!fw_table[i].dest || !fw_table[i].size) { |
| 918 | printf("Error: BIOS binary destination and uncompressed size are required\n"); |
| 919 | free(ctx->rom); |
| 920 | exit(1); |
| 921 | } |
| 922 | if (!fw_table[i].filename && !fw_table[i].src) { |
| 923 | printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); |
| 924 | free(ctx->rom); |
| 925 | exit(1); |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | biosdir->entries[count].type = fw_table[i].type; |
| 930 | biosdir->entries[count].region_type = fw_table[i].region_type; |
| 931 | biosdir->entries[count].dest = fw_table[i].dest ? |
| 932 | fw_table[i].dest : (uint64_t)-1; |
| 933 | biosdir->entries[count].reset = fw_table[i].reset; |
| 934 | biosdir->entries[count].copy = fw_table[i].copy; |
| 935 | biosdir->entries[count].ro = fw_table[i].ro; |
| 936 | biosdir->entries[count].compressed = fw_table[i].zlib; |
| 937 | biosdir->entries[count].inst = fw_table[i].inst; |
| 938 | biosdir->entries[count].subprog = fw_table[i].subpr; |
| 939 | |
| 940 | switch (fw_table[i].type) { |
| 941 | case AMD_BIOS_APOB: |
| 942 | biosdir->entries[count].size = fw_table[i].size; |
| 943 | biosdir->entries[count].source = fw_table[i].src; |
| 944 | break; |
| 945 | case AMD_BIOS_APOB_NV: |
| 946 | if (fw_table[i].src) { |
| 947 | /* If source is given, use that and its size */ |
| 948 | biosdir->entries[count].source = fw_table[i].src; |
| 949 | biosdir->entries[count].size = fw_table[i].size; |
| 950 | } else { |
| 951 | /* Else reserve size bytes within amdfw.rom */ |
| 952 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 953 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 954 | biosdir->entries[count].size = ALIGN( |
| 955 | fw_table[i].size, ERASE_ALIGNMENT); |
| 956 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 957 | biosdir->entries[count].size); |
| 958 | ctx->current = ctx->current |
| 959 | + biosdir->entries[count].size; |
| 960 | } |
| 961 | break; |
| 962 | case AMD_BIOS_BIN: |
| 963 | /* Don't make a 2nd copy, point to the same one */ |
| 964 | if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, |
| 965 | &biosdir->entries[count].source, |
| 966 | &biosdir->entries[count].size)) |
| 967 | break; |
| 968 | |
| 969 | /* level 2, or level 1 and no copy found in level 2 */ |
| 970 | biosdir->entries[count].source = fw_table[i].src; |
| 971 | biosdir->entries[count].dest = fw_table[i].dest; |
| 972 | biosdir->entries[count].size = fw_table[i].size; |
| 973 | |
| 974 | if (!fw_table[i].filename) |
| 975 | break; |
| 976 | |
| 977 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 978 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 979 | if (bytes <= 0) { |
| 980 | free(ctx->rom); |
| 981 | exit(1); |
| 982 | } |
| 983 | |
| 984 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 985 | |
| 986 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 987 | break; |
| 988 | default: /* everything else is copied from input */ |
| 989 | if (fw_table[i].type == AMD_BIOS_APCB || |
| 990 | fw_table[i].type == AMD_BIOS_APCB_BK) |
| 991 | ctx->current = ALIGN( |
| 992 | ctx->current, ERASE_ALIGNMENT); |
| 993 | |
| 994 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 995 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 996 | if (bytes <= 0) { |
| 997 | free(ctx->rom); |
| 998 | exit(1); |
| 999 | } |
| 1000 | |
| 1001 | biosdir->entries[count].size = (uint32_t)bytes; |
| 1002 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 1003 | |
| 1004 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 1005 | break; |
| 1006 | } |
| 1007 | |
| 1008 | count++; |
| 1009 | } |
| 1010 | |
| 1011 | if (biosdir2) { |
| 1012 | biosdir->entries[count].type = AMD_BIOS_L2_PTR; |
| 1013 | biosdir->entries[count].size = |
| 1014 | + MAX_BIOS_ENTRIES |
| 1015 | * sizeof(bios_directory_entry); |
| 1016 | biosdir->entries[count].source = |
| 1017 | BUFF_TO_RUN(*ctx, biosdir2); |
| 1018 | biosdir->entries[count].subprog = 0; |
| 1019 | biosdir->entries[count].inst = 0; |
| 1020 | biosdir->entries[count].copy = 0; |
| 1021 | biosdir->entries[count].compressed = 0; |
| 1022 | biosdir->entries[count].dest = -1; |
| 1023 | biosdir->entries[count].reset = 0; |
| 1024 | biosdir->entries[count].ro = 0; |
| 1025 | count++; |
| 1026 | } |
| 1027 | |
| 1028 | if (count > MAX_BIOS_ENTRIES) { |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 1029 | printf("Error: BIOS entries (%d) exceeds max allowed items " |
| 1030 | "(%d)\n", count, MAX_BIOS_ENTRIES); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1031 | free(ctx->rom); |
| 1032 | exit(1); |
| 1033 | } |
| 1034 | |
| 1035 | fill_dir_header(biosdir, count, cookie); |
| 1036 | } |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1037 | // Unused values: CDEPqR |
| 1038 | static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:"; |
Marc Jones | 90099b6 | 2016-09-20 21:05:45 -0600 | [diff] [blame] | 1039 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1040 | static struct option long_options[] = { |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1041 | {"xhci", required_argument, 0, 'x' }, |
| 1042 | {"imc", required_argument, 0, 'i' }, |
| 1043 | {"gec", required_argument, 0, 'g' }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1044 | /* PSP Directory Table items */ |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1045 | {"combo-capable", no_argument, 0, 'A' }, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1046 | {"multilevel", no_argument, 0, 'M' }, |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1047 | {"subprogram", required_argument, 0, 'S' }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1048 | {"pubkey", required_argument, 0, 'p' }, |
| 1049 | {"bootloader", required_argument, 0, 'b' }, |
| 1050 | {"smufirmware", required_argument, 0, 's' }, |
| 1051 | {"recovery", required_argument, 0, 'r' }, |
| 1052 | {"rtmpubkey", required_argument, 0, 'k' }, |
| 1053 | {"secureos", required_argument, 0, 'c' }, |
| 1054 | {"nvram", required_argument, 0, 'n' }, |
| 1055 | {"securedebug", required_argument, 0, 'd' }, |
| 1056 | {"trustlets", required_argument, 0, 't' }, |
| 1057 | {"trustletkey", required_argument, 0, 'u' }, |
| 1058 | {"smufirmware2", required_argument, 0, 'w' }, |
| 1059 | {"smuscs", required_argument, 0, 'm' }, |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1060 | {"soft-fuse", required_argument, 0, 'T' }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1061 | {"abl-image", required_argument, 0, 'z' }, |
| 1062 | {"sec-gasket", required_argument, 0, 'J' }, |
| 1063 | {"mp2-fw", required_argument, 0, 'B' }, |
| 1064 | {"drv-entry-pts", required_argument, 0, 'K' }, |
| 1065 | {"ikek", required_argument, 0, 'L' }, |
| 1066 | {"s0i3drv", required_argument, 0, 'Y' }, |
| 1067 | {"secdebug", required_argument, 0, 'N' }, |
| 1068 | {"token-unlock", no_argument, 0, 'U' }, |
| 1069 | {"whitelist", required_argument, 0, 'W' }, |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1070 | {"verstage", required_argument, 0, 'Z' }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1071 | /* BIOS Directory Table items */ |
| 1072 | {"instance", required_argument, 0, 'I' }, |
| 1073 | {"apcb", required_argument, 0, 'a' }, |
| 1074 | {"apob-base", required_argument, 0, 'Q' }, |
| 1075 | {"bios-bin", required_argument, 0, 'V' }, |
| 1076 | {"bios-bin-src", required_argument, 0, 'e' }, |
| 1077 | {"bios-bin-dest", required_argument, 0, 'v' }, |
| 1078 | {"bios-uncomp-size", required_argument, 0, 'j' }, |
| 1079 | {"pmu-inst", required_argument, 0, 'y' }, |
| 1080 | {"pmu-data", required_argument, 0, 'G' }, |
| 1081 | {"ucode", required_argument, 0, 'O' }, |
| 1082 | {"mp2-config", required_argument, 0, 'X' }, |
| 1083 | {"apob-nv-base", required_argument, 0, 'F' }, |
| 1084 | {"apob-nv-size", required_argument, 0, 'H' }, |
| 1085 | /* other */ |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1086 | {"output", required_argument, 0, 'o' }, |
| 1087 | {"flashsize", required_argument, 0, 'f' }, |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1088 | {"location", required_argument, 0, 'l' }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1089 | {"help", no_argument, 0, 'h' }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1090 | {NULL, 0, 0, 0 } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1091 | }; |
| 1092 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1093 | static void register_fw_fuse(char *str) |
| 1094 | { |
| 1095 | int i; |
| 1096 | |
| 1097 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1098 | if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) |
| 1099 | continue; |
| 1100 | |
| 1101 | amd_psp_fw_table[i].other = strtoull(str, NULL, 16); |
| 1102 | return; |
| 1103 | } |
| 1104 | } |
| 1105 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1106 | static void register_fw_token_unlock(void) |
| 1107 | { |
| 1108 | int i; |
| 1109 | |
| 1110 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1111 | if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) |
| 1112 | continue; |
| 1113 | |
| 1114 | amd_psp_fw_table[i].other = 1; |
| 1115 | return; |
| 1116 | } |
| 1117 | } |
| 1118 | |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1119 | static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1120 | { |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1121 | unsigned int i; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1122 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 1123 | for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1124 | if (amd_fw_table[i].type == type) { |
| 1125 | amd_fw_table[i].filename = filename; |
| 1126 | return; |
| 1127 | } |
| 1128 | } |
| 1129 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1130 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1131 | if (amd_psp_fw_table[i].type != type) |
| 1132 | continue; |
| 1133 | |
| 1134 | if (amd_psp_fw_table[i].subprog == sub) { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1135 | amd_psp_fw_table[i].filename = filename; |
| 1136 | return; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1137 | } |
| 1138 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1139 | } |
| 1140 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1141 | static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) |
| 1142 | { |
| 1143 | int i; |
| 1144 | |
| 1145 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1146 | if (amd_bios_table[i].type == type |
| 1147 | && amd_bios_table[i].inst == ins |
| 1148 | && amd_bios_table[i].subpr == sub) { |
| 1149 | amd_bios_table[i].filename = name; |
| 1150 | return; |
| 1151 | } |
| 1152 | } |
| 1153 | } |
| 1154 | |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 1155 | static void register_fw_addr(amd_bios_type type, char *src_str, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1156 | char *dst_str, char *size_str) |
| 1157 | { |
| 1158 | int i; |
| 1159 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1160 | if (amd_bios_table[i].type != type) |
| 1161 | continue; |
| 1162 | |
| 1163 | if (src_str) |
| 1164 | amd_bios_table[i].src = strtoull(src_str, NULL, 16); |
| 1165 | if (dst_str) |
| 1166 | amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1167 | if (size_str) |
| 1168 | amd_bios_table[i].size = strtoul(size_str, NULL, 16); |
| 1169 | |
| 1170 | return; |
| 1171 | } |
| 1172 | } |
| 1173 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1174 | int main(int argc, char **argv) |
| 1175 | { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1176 | int c; |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1177 | int retval = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1178 | char *tmp; |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1179 | char *rom = NULL; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1180 | embedded_firmware *amd_romsig; |
| 1181 | psp_directory_table *pspdir; |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1182 | int comboable = 0; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1183 | int fuse_defined = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1184 | int targetfd; |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1185 | char *output = NULL; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1186 | context ctx = { |
| 1187 | .rom_size = CONFIG_ROM_SIZE, |
| 1188 | }; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1189 | /* Values cleared after each firmware or parameter, regardless if N/A */ |
| 1190 | uint8_t sub = 0, instance = 0; |
| 1191 | int abl_image = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1192 | uint32_t dir_location = 0; |
| 1193 | uint32_t romsig_offset; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1194 | uint32_t rom_base_address; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1195 | int multi = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1196 | |
| 1197 | while (1) { |
| 1198 | int optindex = 0; |
| 1199 | |
| 1200 | c = getopt_long(argc, argv, optstring, long_options, &optindex); |
| 1201 | |
| 1202 | if (c == -1) |
| 1203 | break; |
| 1204 | |
| 1205 | switch (c) { |
| 1206 | case 'x': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1207 | register_fw_filename(AMD_FW_XHCI, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1208 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1209 | break; |
| 1210 | case 'i': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1211 | register_fw_filename(AMD_FW_IMC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1212 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1213 | break; |
| 1214 | case 'g': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1215 | register_fw_filename(AMD_FW_GEC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1216 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1217 | break; |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1218 | case 'A': |
| 1219 | comboable = 1; |
| 1220 | break; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1221 | case 'M': |
| 1222 | multi = 1; |
| 1223 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1224 | case 'U': |
| 1225 | register_fw_token_unlock(); |
| 1226 | sub = instance = 0; |
| 1227 | break; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1228 | case 'S': |
| 1229 | sub = (uint8_t)strtoul(optarg, &tmp, 16); |
| 1230 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1231 | case 'I': |
| 1232 | instance = strtoul(optarg, &tmp, 16); |
| 1233 | break; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1234 | case 'p': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1235 | register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1236 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1237 | break; |
| 1238 | case 'b': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1239 | register_fw_filename(AMD_FW_PSP_BOOTLOADER, |
| 1240 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1241 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1242 | break; |
| 1243 | case 's': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1244 | register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, |
| 1245 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1246 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1247 | break; |
| 1248 | case 'r': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1249 | register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1250 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1251 | break; |
| 1252 | case 'k': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1253 | register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, |
| 1254 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1255 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1256 | break; |
| 1257 | case 'c': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1258 | register_fw_filename(AMD_FW_PSP_SECURED_OS, |
| 1259 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1260 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1261 | break; |
| 1262 | case 'n': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1263 | register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1264 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1265 | break; |
| 1266 | case 'd': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1267 | register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, |
| 1268 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1269 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1270 | break; |
| 1271 | case 't': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1272 | register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1273 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1274 | break; |
| 1275 | case 'u': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1276 | register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, |
| 1277 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1278 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1279 | break; |
| 1280 | case 'w': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1281 | register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, |
| 1282 | sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1283 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1284 | break; |
| 1285 | case 'm': |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1286 | register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1287 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1288 | break; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1289 | case 'T': |
| 1290 | register_fw_fuse(optarg); |
| 1291 | fuse_defined = 1; |
| 1292 | sub = 0; |
| 1293 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1294 | case 'a': |
| 1295 | register_bdt_data(AMD_BIOS_APCB, sub, instance, optarg); |
| 1296 | register_bdt_data(AMD_BIOS_APCB_BK, sub, |
| 1297 | instance, optarg); |
| 1298 | sub = instance = 0; |
| 1299 | break; |
| 1300 | case 'Q': |
| 1301 | /* APOB destination */ |
| 1302 | register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); |
| 1303 | sub = instance = 0; |
| 1304 | break; |
| 1305 | case 'F': |
| 1306 | /* APOB NV source */ |
| 1307 | register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); |
| 1308 | sub = instance = 0; |
| 1309 | break; |
| 1310 | case 'H': |
| 1311 | /* APOB NV size */ |
| 1312 | register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); |
| 1313 | sub = instance = 0; |
| 1314 | break; |
| 1315 | case 'V': |
| 1316 | register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); |
| 1317 | sub = instance = 0; |
| 1318 | break; |
| 1319 | case 'e': |
| 1320 | /* BIOS source */ |
| 1321 | register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); |
| 1322 | sub = instance = 0; |
| 1323 | break; |
| 1324 | case 'v': |
| 1325 | /* BIOS destination */ |
| 1326 | register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); |
| 1327 | sub = instance = 0; |
| 1328 | break; |
| 1329 | case 'j': |
| 1330 | /* BIOS destination size */ |
| 1331 | register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); |
| 1332 | sub = instance = 0; |
| 1333 | break; |
| 1334 | case 'y': |
| 1335 | register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg); |
| 1336 | sub = instance = 0; |
| 1337 | break; |
| 1338 | case 'G': |
| 1339 | register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg); |
| 1340 | sub = instance = 0; |
| 1341 | break; |
| 1342 | case 'O': |
| 1343 | register_bdt_data(AMD_BIOS_UCODE, sub, |
| 1344 | instance, optarg); |
| 1345 | sub = instance = 0; |
| 1346 | break; |
| 1347 | case 'J': |
| 1348 | register_fw_filename(AMD_SEC_GASKET, sub, optarg); |
| 1349 | sub = instance = 0; |
| 1350 | break; |
| 1351 | case 'B': |
| 1352 | register_fw_filename(AMD_MP2_FW, sub, optarg); |
| 1353 | sub = instance = 0; |
| 1354 | break; |
| 1355 | case 'z': |
| 1356 | register_fw_filename(AMD_ABL0 + abl_image++, |
| 1357 | sub, optarg); |
| 1358 | sub = instance = 0; |
| 1359 | break; |
| 1360 | case 'X': |
| 1361 | register_bdt_data(AMD_BIOS_MP2_CFG, sub, |
| 1362 | instance, optarg); |
| 1363 | sub = instance = 0; |
| 1364 | break; |
| 1365 | case 'K': |
| 1366 | register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg); |
| 1367 | sub = instance = 0; |
| 1368 | break; |
| 1369 | case 'L': |
| 1370 | register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg); |
| 1371 | sub = instance = 0; |
| 1372 | break; |
| 1373 | case 'Y': |
| 1374 | register_fw_filename(AMD_S0I3_DRIVER, sub, optarg); |
| 1375 | sub = instance = 0; |
| 1376 | break; |
| 1377 | case 'N': |
| 1378 | register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg); |
| 1379 | sub = instance = 0; |
| 1380 | break; |
| 1381 | case 'W': |
| 1382 | register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); |
| 1383 | sub = instance = 0; |
| 1384 | break; |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1385 | case 'Z': |
| 1386 | register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); |
| 1387 | sub = instance = 0; |
| 1388 | break; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1389 | case 'o': |
| 1390 | output = optarg; |
| 1391 | break; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1392 | case 'f': |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1393 | ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1394 | if (*tmp != '\0') { |
| 1395 | printf("Error: ROM size specified" |
| 1396 | " incorrectly (%s)\n\n", optarg); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1397 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1398 | } |
| 1399 | break; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1400 | case 'l': |
| 1401 | dir_location = (uint32_t)strtoul(optarg, &tmp, 16); |
| 1402 | if (*tmp != '\0') { |
| 1403 | printf("Error: Directory Location specified" |
| 1404 | " incorrectly (%s)\n\n", optarg); |
| 1405 | retval = 1; |
| 1406 | } |
| 1407 | break; |
| 1408 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1409 | case 'h': |
| 1410 | usage(); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1411 | return 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1412 | default: |
| 1413 | break; |
| 1414 | } |
| 1415 | } |
| 1416 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1417 | if (!fuse_defined) |
| 1418 | register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); |
| 1419 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1420 | if (!output) { |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1421 | printf("Error: Output value is not specified.\n\n"); |
| 1422 | retval = 1; |
| 1423 | } |
| 1424 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1425 | if (ctx.rom_size % 1024 != 0) { |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1426 | printf("Error: ROM Size (%d bytes) should be a multiple of" |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1427 | " 1024 bytes.\n\n", ctx.rom_size); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1428 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1429 | } |
| 1430 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1431 | if (ctx.rom_size < MIN_ROM_KB * 1024) { |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1432 | printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n", |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1433 | ctx.rom_size / 1024, MIN_ROM_KB); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1434 | retval = 1; |
| 1435 | } |
| 1436 | |
| 1437 | if (retval) { |
| 1438 | usage(); |
| 1439 | return retval; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1440 | } |
| 1441 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1442 | printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1443 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1444 | rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1445 | if (dir_location && (dir_location < rom_base_address)) { |
| 1446 | printf("Error: Directory location outside of ROM.\n\n"); |
| 1447 | return 1; |
| 1448 | } |
| 1449 | |
| 1450 | switch (dir_location) { |
| 1451 | case 0: /* Fall through */ |
| 1452 | case 0xFFFA0000: /* Fall through */ |
| 1453 | case 0xFFF20000: /* Fall through */ |
| 1454 | case 0xFFE20000: /* Fall through */ |
| 1455 | case 0xFFC20000: /* Fall through */ |
| 1456 | case 0xFF820000: /* Fall through */ |
| 1457 | case 0xFF020000: /* Fall through */ |
| 1458 | break; |
| 1459 | default: |
| 1460 | printf("Error: Invalid Directory location.\n"); |
| 1461 | printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); |
| 1462 | printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); |
| 1463 | return 1; |
| 1464 | } |
| 1465 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1466 | ctx.rom = malloc(ctx.rom_size); |
| 1467 | if (!ctx.rom) { |
| 1468 | printf("Error: Failed to allocate memory\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1469 | return 1; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1470 | } |
| 1471 | memset(ctx.rom, 0xFF, ctx.rom_size); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1472 | |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1473 | if (dir_location) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1474 | romsig_offset = ctx.current = dir_location - rom_base_address; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1475 | else |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1476 | romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; |
| 1477 | printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", |
| 1478 | RUN_CURRENT(ctx)); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1479 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1480 | amd_romsig = BUFF_OFFSET(ctx, romsig_offset); |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1481 | amd_romsig->signature = EMBEDDED_FW_SIGNATURE; |
| 1482 | amd_romsig->imc_entry = 0; |
| 1483 | amd_romsig->gec_entry = 0; |
| 1484 | amd_romsig->xhci_entry = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1485 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1486 | integrate_firmwares(&ctx, amd_romsig, amd_fw_table); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1487 | |
Patrick Georgi | 900a254 | 2020-02-17 16:52:40 +0100 | [diff] [blame] | 1488 | ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1489 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1490 | if (multi) { |
| 1491 | /* Do 2nd PSP directory followed by 1st */ |
| 1492 | psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi); |
| 1493 | integrate_psp_firmwares(&ctx, pspdir2, 0, |
| 1494 | amd_psp_fw_table, PSPL2_COOKIE); |
| 1495 | |
| 1496 | pspdir = new_psp_dir(&ctx, multi); |
| 1497 | integrate_psp_firmwares(&ctx, pspdir, pspdir2, |
| 1498 | amd_psp_fw_table, PSP_COOKIE); |
| 1499 | } else { |
| 1500 | /* flat: PSP 1 cookie and no pointer to 2nd table */ |
| 1501 | pspdir = new_psp_dir(&ctx, multi); |
| 1502 | integrate_psp_firmwares(&ctx, pspdir, 0, |
| 1503 | amd_psp_fw_table, PSP_COOKIE); |
| 1504 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1505 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1506 | if (comboable) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1507 | amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1508 | else |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1509 | amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1510 | |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1511 | #if PSP_COMBO |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1512 | psp_combo_directory *combo_dir = new_combo_dir(&ctx); |
| 1513 | amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir); |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1514 | /* 0 -Compare PSP ID, 1 -Compare chip family ID */ |
| 1515 | combo_dir->entries[0].id_sel = 0; |
| 1516 | /* TODO: PSP ID. Documentation is needed. */ |
| 1517 | combo_dir->entries[0].id = 0x10220B00; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1518 | combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1519 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1520 | combo_dir->header.lookup = 1; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 1521 | fill_dir_header(combo_dir, 1, PSP2_COOKIE); |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1522 | #endif |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1523 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1524 | if (have_bios_tables(amd_bios_table)) { |
| 1525 | bios_directory_table *biosdir; |
| 1526 | if (multi) { |
| 1527 | /* Do 2nd level BIOS directory followed by 1st */ |
| 1528 | bios_directory_table *biosdir2 = |
| 1529 | new_bios_dir(&ctx, multi); |
| 1530 | integrate_bios_firmwares(&ctx, biosdir2, 0, |
| 1531 | amd_bios_table, BDT2_COOKIE); |
| 1532 | |
| 1533 | biosdir = new_bios_dir(&ctx, multi); |
| 1534 | integrate_bios_firmwares(&ctx, biosdir, biosdir2, |
| 1535 | amd_bios_table, BDT1_COOKIE); |
| 1536 | } else { |
| 1537 | /* flat: BDT1 cookie and no pointer to 2nd table */ |
| 1538 | biosdir = new_bios_dir(&ctx, multi); |
| 1539 | integrate_bios_firmwares(&ctx, biosdir, 0, |
| 1540 | amd_bios_table, BDT1_COOKIE); |
| 1541 | } |
| 1542 | amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); |
| 1543 | } |
| 1544 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1545 | targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1546 | if (targetfd >= 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1547 | write(targetfd, amd_romsig, ctx.current - romsig_offset); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1548 | close(targetfd); |
| 1549 | } else { |
| 1550 | printf("Error: could not open file: %s\n", output); |
| 1551 | retval = 1; |
| 1552 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1553 | |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1554 | free(rom); |
| 1555 | return retval; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1556 | } |