Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | config SOC_INTEL_ELKHARTLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Elkhartlake support |
| 5 | |
| 6 | if SOC_INTEL_ELKHARTLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 11 | select ARCH_X86 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 13 | select CACHE_MRC_SETTINGS |
| 14 | select CPU_INTEL_COMMON |
| 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
| 18 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 19 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 20 | select GENERIC_GPIO_LIB |
| 21 | select HAVE_FSP_GOP |
| 22 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 23 | select HAVE_SMI_HANDLER |
| 24 | select IDT_IN_EVERY_STAGE |
| 25 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
| 26 | select INTEL_GMA_ACPI |
| 27 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 28 | select MP_SERVICES_PPI_V1 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 29 | select MRC_SETTINGS_PROTECT |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 30 | select PARALLEL_MP_AP_WORK |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 31 | select PLATFORM_USES_FSP2_1 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 32 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 33 | select SOC_INTEL_COMMON |
| 34 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 35 | select SOC_INTEL_COMMON_BLOCK |
| 36 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | 02275be | 2020-11-12 23:50:37 +0100 | [diff] [blame] | 37 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 38 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 46c5f8f | 2021-07-01 08:45:47 -0600 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_CAR |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 43 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 44 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 47 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 48 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| 50 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_SA |
| 52 | select SOC_INTEL_COMMON_BLOCK_SCS |
| 53 | select SOC_INTEL_COMMON_BLOCK_SMM |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_FSP_RESET |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_PCH_BASE |
| 57 | select SOC_INTEL_COMMON_RESET |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 58 | select SSE2 |
| 59 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 60 | select TSC_MONOTONIC_TIMER |
| 61 | select UDELAY_TSC |
| 62 | select UDK_202005_BINDING |
| 63 | select DISPLAY_FSP_VERSION_INFO |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 64 | select HAVE_INTEL_FSP_REPO |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 65 | |
| 66 | config MAX_CPUS |
| 67 | int |
| 68 | default 4 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 69 | |
| 70 | config DCACHE_RAM_BASE |
| 71 | default 0xfef00000 |
| 72 | |
| 73 | config DCACHE_RAM_SIZE |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 74 | default 0xc0000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 75 | help |
| 76 | The size of the cache-as-ram region required during bootblock |
| 77 | and/or romstage. |
| 78 | |
| 79 | config DCACHE_BSP_STACK_SIZE |
| 80 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 81 | default 0x30000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 82 | help |
| 83 | The amount of anticipated stack usage in CAR by bootblock and |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 84 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 85 | sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 86 | |
| 87 | config FSP_TEMP_RAM_SIZE |
| 88 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 89 | default 0x40000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 90 | help |
| 91 | The amount of anticipated heap usage in CAR by FSP. |
| 92 | Refer to Platform FSP integration guide document to know |
| 93 | the exact FSP requirement for Heap setup. |
| 94 | |
| 95 | config IFD_CHIPSET |
| 96 | string |
| 97 | default "ehl" |
| 98 | |
| 99 | config IED_REGION_SIZE |
| 100 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 101 | default 0x0 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 102 | |
| 103 | config HEAP_SIZE |
| 104 | hex |
| 105 | default 0x8000 |
| 106 | |
| 107 | config MAX_ROOT_PORTS |
| 108 | int |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 109 | default 7 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 110 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 111 | config MAX_SATA_PORTS |
| 112 | int |
| 113 | default 2 |
| 114 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 115 | config MAX_PCIE_CLOCK_SRC |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 116 | int |
| 117 | default 6 |
| 118 | |
| 119 | config SMM_TSEG_SIZE |
| 120 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 121 | default 0x1000000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 122 | |
| 123 | config SMM_RESERVED_SIZE |
| 124 | hex |
| 125 | default 0x200000 |
| 126 | |
| 127 | config PCR_BASE_ADDRESS |
| 128 | hex |
| 129 | default 0xfd000000 |
| 130 | help |
| 131 | This option allows you to select MMIO Base Address of sideband bus. |
| 132 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 133 | config ECAM_MMCONF_BASE_ADDRESS |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 134 | default 0xc0000000 |
| 135 | |
| 136 | config CPU_BCLK_MHZ |
| 137 | int |
| 138 | default 100 |
| 139 | |
| 140 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 141 | int |
| 142 | default 120 |
| 143 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 144 | config CPU_XTAL_HZ |
| 145 | default 38400000 |
| 146 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 147 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 148 | int |
| 149 | default 133 |
| 150 | |
| 151 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 152 | int |
| 153 | default 3 |
| 154 | |
| 155 | config SOC_INTEL_I2C_DEV_MAX |
| 156 | int |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 157 | default 8 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 158 | |
| 159 | config SOC_INTEL_UART_DEV_MAX |
| 160 | int |
| 161 | default 3 |
| 162 | |
| 163 | config CONSOLE_UART_BASE_ADDRESS |
| 164 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 165 | default 0xfe042000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 166 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 167 | |
| 168 | # Clock divider parameters for 115200 baud rate |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 169 | # Baudrate = (UART source clock * M) /(N *16) |
| 170 | # EHL UART source clock: 120MHz |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 171 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 172 | hex |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 173 | default 0x25a |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 174 | |
| 175 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 176 | hex |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 177 | default 0x7fff |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 178 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 179 | config VBOOT |
| 180 | select VBOOT_SEPARATE_VERSTAGE |
| 181 | select VBOOT_MUST_REQUEST_DISPLAY |
| 182 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 183 | select VBOOT_VBNV_CMOS |
| 184 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 185 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 186 | config CBFS_SIZE |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 187 | default 0x200000 |
| 188 | |
| 189 | config FSP_HEADER_PATH |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 190 | default "3rdparty/fsp/ElkhartLakeFspBinPkg/Include/" |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 191 | |
| 192 | config FSP_FD_PATH |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 193 | string |
| 194 | depends on FSP_USE_REPO |
| 195 | default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin" |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 196 | |
| 197 | config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT |
| 198 | int "Debug Consent for EHL" |
| 199 | # USB DBC is more common for developers so make this default to 3 if |
| 200 | # SOC_INTEL_DEBUG_CONSENT=y |
| 201 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 202 | default 0 |
| 203 | help |
| 204 | This is to control debug interface on SOC. |
| 205 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 206 | PlatformDebugConsent in FspmUpd.h has the details. |
| 207 | |
| 208 | Desired platform debug type are |
| 209 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 210 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 211 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 212 | |
| 213 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 214 | hex |
| 215 | default 0x1400 |
| 216 | endif |