| Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #include <soc/irq.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/pm.h> |
| 24 | |
| 25 | #define PCI_DEV_PIRQ_ROUTES \ |
| 26 | PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ |
| 27 | PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ |
| 28 | PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ |
| 29 | PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ |
| 30 | PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ |
| 31 | PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ |
| 32 | PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ |
| 33 | PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ |
| 34 | PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ |
| 35 | PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ |
| 36 | PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ |
| 37 | PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ |
| 38 | PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) |
| 39 | |
| 40 | #define PIRQ_PIC_ROUTES \ |
| 41 | PIRQ_PIC(A, DISABLE), \ |
| 42 | PIRQ_PIC(B, DISABLE), \ |
| 43 | PIRQ_PIC(C, DISABLE), \ |
| 44 | PIRQ_PIC(D, DISABLE), \ |
| 45 | PIRQ_PIC(E, DISABLE), \ |
| 46 | PIRQ_PIC(F, DISABLE), \ |
| 47 | PIRQ_PIC(G, DISABLE), \ |
| 48 | PIRQ_PIC(H, DISABLE) |
| 49 | |
| 50 | /* CORE bank DIRQs - up to 16 supported */ |
| 51 | #define TPAD_IRQ_OFFSET 0 |
| 52 | #define TOUCH_IRQ_OFFSET 1 |
| 53 | #define I8042_IRQ_OFFSET 2 |
| 54 | #define ALS_IRQ_OFFSET 3 |
| 55 | /* Corresponding SCORE GPIO pins */ |
| 56 | #define TPAD_IRQ_GPIO 55 |
| 57 | #define TOUCH_IRQ_GPIO 72 |
| 58 | #define I8042_IRQ_GPIO 101 |
| 59 | #define ALS_IRQ_GPIO 70 |
| 60 | |
| 61 | /* SUS bank DIRQs - up to 16 supported */ |
| 62 | #define CODEC_IRQ_OFFSET 0 |
| 63 | /* Corresponding SUS GPIO pins */ |
| 64 | #define CODEC_IRQ_GPIO 9 |