blob: b773b09107c732e3f47a02ba0dc7933f0a388887 [file] [log] [blame]
Lee Leahy5cb9dda2015-05-01 10:34:54 -07001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5## Copyright (C) 2015 Intel Corp.
6##
7## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc.
19##
20
21# -----------------------------------------------------------------
22entries
23
24#start-bit length config config-ID name
25#0 8 r 0 seconds
26#8 8 r 0 alarm_seconds
27#16 8 r 0 minutes
28#24 8 r 0 alarm_minutes
29#32 8 r 0 hours
30#40 8 r 0 alarm_hours
31#48 8 r 0 day_of_week
32#56 8 r 0 day_of_month
33#64 8 r 0 month
34#72 8 r 0 year
35# -----------------------------------------------------------------
36# Status Register A
37#80 4 r 0 rate_select
38#84 3 r 0 REF_Clock
39#87 1 r 0 UIP
40# -----------------------------------------------------------------
41# Status Register B
42#88 1 r 0 auto_switch_DST
43#89 1 r 0 24_hour_mode
44#90 1 r 0 binary_values_enable
45#91 1 r 0 square-wave_out_enable
46#92 1 r 0 update_finished_enable
47#93 1 r 0 alarm_interrupt_enable
48#94 1 r 0 periodic_interrupt_enable
49#95 1 r 0 disable_clock_updates
50# -----------------------------------------------------------------
51# Status Register C
52#96 4 r 0 status_c_rsvd
53#100 1 r 0 uf_flag
54#101 1 r 0 af_flag
55#102 1 r 0 pf_flag
56#103 1 r 0 irqf_flag
57# -----------------------------------------------------------------
58# Status Register D
59#104 7 r 0 status_d_rsvd
60#111 1 r 0 valid_cmos_ram
61# -----------------------------------------------------------------
62# Diagnostic Status Register
63#112 8 r 0 diag_rsvd1
64
65# -----------------------------------------------------------------
660 120 r 0 reserved_memory
67#120 264 r 0 unused
68
69# -----------------------------------------------------------------
70# RTC_BOOT_BYTE (coreboot hardcoded)
71384 1 e 4 boot_option
72385 1 e 4 last_boot
73388 4 r 0 reboot_bits
74#390 2 r 0 unused?
75
76# -----------------------------------------------------------------
77# coreboot config options: console
78392 3 e 5 baud_rate
79395 4 e 6 debug_level
80#399 1 r 0 unused
81
82# coreboot config options: cpu
83400 1 e 2 hyper_threading
84#401 7 r 0 unused
85
86# coreboot config options: southbridge
87408 1 e 1 nmi
88409 2 e 7 power_on_after_fail
89#411 5 r 0 unused
90
91# coreboot config options: bootloader
92#Used by ChromeOS:
93416 128 r 0 vbnv
94#544 440 r 0 unused
95
96# SandyBridge MRC Scrambler Seed values
97896 32 r 0 mrc_scrambler_seed
98928 32 r 0 mrc_scrambler_seed_s3
99
100# coreboot config options: check sums
101984 16 h 0 check_sum
102#1000 24 r 0 amd_reserved
103
104# -----------------------------------------------------------------
105
106enumerations
107
108#ID value text
1091 0 Disable
1101 1 Enable
1112 0 Enable
1122 1 Disable
1134 0 Fallback
1144 1 Normal
1155 0 115200
1165 1 57600
1175 2 38400
1185 3 19200
1195 4 9600
1205 5 4800
1215 6 2400
1225 7 1200
1236 1 Emergency
1246 2 Alert
1256 3 Critical
1266 4 Error
1276 5 Warning
1286 6 Notice
1296 7 Info
1306 8 Debug
1316 9 Spew
1327 0 Disable
1337 1 Enable
1347 2 Keep
135# -----------------------------------------------------------------
136checksums
137
138checksum 392 415 984
139
140