Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | ebace9f | 2018-05-26 18:56:17 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | 5c2594e | 2021-06-08 10:47:24 +0300 | [diff] [blame^] | 3 | #include <arch/ioapic.h> |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
Steven J. Magnani | 09e4ef6 | 2005-09-14 13:56:25 +0000 | [diff] [blame] | 9 | #include <assert.h> |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 10 | #include "82870.h" |
| 11 | |
Steven J. Magnani | 09e4ef6 | 2005-09-14 13:56:25 +0000 | [diff] [blame] | 12 | static int num_p64h2_ioapics = 0; |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 13 | |
Elyes HAOUAS | 17c59f5 | 2018-05-13 13:38:38 +0200 | [diff] [blame] | 14 | static void p64h2_ioapic_enable(struct device *dev) |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 15 | { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 16 | /* We have to enable MEM and Bus Master for IOAPIC */ |
| 17 | uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 18 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 19 | pci_write_config16(dev, PCI_COMMAND, command); |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 20 | } |
| 21 | |
Uwe Hermann | b69cb5a | 2010-10-26 22:46:43 +0000 | [diff] [blame] | 22 | /** |
| 23 | * Configure one of the IOAPICs in a P64H2. |
| 24 | * |
| 25 | * Note that a PCI bus scan will detect both IOAPICs, so this function |
| 26 | * will be called twice for each P64H2 in the system. |
| 27 | * |
| 28 | * @param dev PCI bus/device/function of P64H2 IOAPIC. |
| 29 | * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0. |
| 30 | */ |
Elyes HAOUAS | 17c59f5 | 2018-05-13 13:38:38 +0200 | [diff] [blame] | 31 | static void p64h2_ioapic_init(struct device *dev) |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 32 | { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 33 | uint32_t memoryBase; |
| 34 | int apic_index, apic_id; |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 35 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 36 | apic_index = num_p64h2_ioapics; |
| 37 | num_p64h2_ioapics++; |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 38 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 39 | // A note on IOAPIC addresses: |
| 40 | // 0 and 1 are used for the local APICs of the dual virtual |
| 41 | // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb). |
| 42 | // 6 and 7 are used for the local APICs of the dual virtual |
| 43 | // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb). |
| 44 | // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c) |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 45 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 46 | // Map APIC index into APIC ID |
| 47 | // IDs 3, 4, 5, and 8+ are available (see above note) |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 48 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 49 | if (apic_index < 3) |
| 50 | apic_id = apic_index + 3; |
| 51 | else |
| 52 | apic_id = apic_index + 5; |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 53 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 54 | ASSERT(apic_id < 16); // ID is only 4 bits |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 55 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 56 | // Read the MBAR address for setting up the IOAPIC in memory space |
| 57 | // NOTE: this address was assigned during enumeration of the bus |
Steven J. Magnani | 09e4ef6 | 2005-09-14 13:56:25 +0000 | [diff] [blame] | 58 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 59 | memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Steven J. Magnani | 09e4ef6 | 2005-09-14 13:56:25 +0000 | [diff] [blame] | 60 | |
Kyösti Mälkki | 5c2594e | 2021-06-08 10:47:24 +0300 | [diff] [blame^] | 61 | set_ioapic_id((void *)memoryBase, apic_id); |
Steven J. Magnani | 09e4ef6 | 2005-09-14 13:56:25 +0000 | [diff] [blame] | 62 | |
Kyösti Mälkki | 5c2594e | 2021-06-08 10:47:24 +0300 | [diff] [blame^] | 63 | // Use Processor System Bus to deliver interrupts |
| 64 | ioapic_set_boot_config((void *)memoryBase, true); |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | static struct device_operations ioapic_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 68 | .read_resources = pci_dev_read_resources, |
| 69 | .set_resources = pci_dev_set_resources, |
| 70 | .enable_resources = pci_dev_enable_resources, |
| 71 | .init = p64h2_ioapic_init, |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 72 | .enable = p64h2_ioapic_enable, |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 73 | }; |
| 74 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 75 | static const struct pci_driver ioapic_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 76 | .ops = &ioapic_ops, |
| 77 | .vendor = PCI_VENDOR_ID_INTEL, |
| 78 | .device = PCI_DEVICE_ID_INTEL_82870_1E0, |
Yinghai Lu | 70093f7 | 2004-07-01 03:55:03 +0000 | [diff] [blame] | 79 | |
| 80 | }; |