Jonathan Zhang | 9ab4dc3 | 2020-02-24 17:39:05 -0800 | [diff] [blame] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPMUPD_H__ |
| 34 | #define __FSPMUPD_H__ |
| 35 | |
| 36 | #include <FspUpd.h> |
| 37 | |
| 38 | #pragma pack(1) |
| 39 | |
| 40 | /** |
| 41 | FSP Header Version Number |
| 42 | **/ |
| 43 | #define FSP_UPD_VERSION (0x1947) |
| 44 | |
| 45 | #define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */ |
| 46 | #define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */ |
| 47 | |
Jonathan Zhang | e425a09 | 2020-03-04 09:38:06 -0800 | [diff] [blame] | 48 | #define HIDE 1 |
| 49 | #define NOT_HIDE 0 |
| 50 | |
| 51 | #define IIO_BIFURCATE_AUTO 0xFF |
| 52 | |
| 53 | /* Ports 1D-1A, 2D-2A, 3D-3A */ |
| 54 | #define IIO_BIFURCATE_x4x4x4x4 0 |
| 55 | #define IIO_BIFURCATE_x4x4xxx8 1 |
| 56 | #define IIO_BIFURCATE_xxx8x4x4 2 |
| 57 | #define IIO_BIFURCATE_xxx8xxx8 3 |
| 58 | #define IIO_BIFURCATE_xxxxxx16 4 |
| 59 | #define IIO_BIFURCATE_xxxxxxxx 0xF |
| 60 | |
| 61 | |
| 62 | typedef enum { |
| 63 | IioPortA = 0, |
| 64 | IioPortB = 1, |
| 65 | IioPortC = 2, |
| 66 | IioPortD = 3 |
| 67 | } IIO_PORTS; |
| 68 | |
| 69 | /** |
| 70 | * Enums and Macro definitions needed for reference RVP and CRB |
| 71 | * table declarations |
| 72 | **/ |
| 73 | typedef enum { |
| 74 | Iio_Socket0 = 0, |
| 75 | Iio_Socket1, |
| 76 | Iio_Socket2, |
| 77 | Iio_Socket3, |
| 78 | Iio_Socket4, |
| 79 | Iio_Socket5, |
| 80 | Iio_Socket6, |
| 81 | Iio_Socket7 |
| 82 | } IIO_SOCKETS; |
| 83 | |
| 84 | typedef enum { |
| 85 | Iio_Iou0 = 0, |
| 86 | Iio_Iou1, |
| 87 | Iio_Iou2, |
| 88 | Iio_Mcp0, |
| 89 | Iio_Mcp1, |
| 90 | Iio_IouMax |
| 91 | } IIO_IOUS; |
| 92 | |
Jonathan Zhang | 9ab4dc3 | 2020-02-24 17:39:05 -0800 | [diff] [blame] | 93 | /** |
| 94 | IIO PCIe Ports |
| 95 | **/ |
| 96 | typedef enum { |
| 97 | PORT_0 = 0, |
| 98 | // IOU2 |
| 99 | PORT_1A, |
| 100 | PORT_1B, |
| 101 | PORT_1C, |
| 102 | PORT_1D, |
| 103 | // IOU0 |
| 104 | PORT_2A, |
| 105 | PORT_2B, |
| 106 | PORT_2C, |
| 107 | PORT_2D, |
| 108 | // IOU1 |
| 109 | PORT_3A, |
| 110 | PORT_3B, |
| 111 | PORT_3C, |
| 112 | PORT_3D, |
| 113 | // MCP0 |
| 114 | PORT_4A, |
| 115 | PORT_4B, |
| 116 | PORT_4C, |
| 117 | PORT_4D, |
| 118 | // MCP1 |
| 119 | PORT_5A, |
| 120 | PORT_5B, |
| 121 | PORT_5C, |
| 122 | PORT_5D, |
| 123 | MAX_PORTS |
| 124 | } PCIE_PORTS; |
| 125 | |
| 126 | /** |
| 127 | IIO Stacks |
| 128 | **/ |
| 129 | typedef enum { |
| 130 | CSTACK = 0, |
| 131 | PSTACK0, |
| 132 | PSTACK1, |
| 133 | PSTACK2, |
| 134 | PSTACK3, |
| 135 | PSTACK4, |
| 136 | MAX_STACKS |
| 137 | } IIO_STACKS; |
| 138 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame^] | 139 | #define IioStack0 CSTACK |
| 140 | /* MAX_LOGIC_IIO_STACK is needed by uncore_acpi.c, define the same value from nb_acpi.c for |
| 141 | Skylake-SP to keep the same behavior. */ |
| 142 | #define MAX_LOGIC_IIO_STACK PSTACK2 |
| 143 | |
Jonathan Zhang | 9ab4dc3 | 2020-02-24 17:39:05 -0800 | [diff] [blame] | 144 | /** |
| 145 | NTB Per Port Definition |
| 146 | **/ |
| 147 | typedef enum { |
| 148 | NTB_PORT_TRANSPARENT = 0, |
| 149 | NTB_PORT_NTB_NTB |
| 150 | } NTB_PPD; |
| 151 | |
| 152 | /** |
| 153 | NTB Upstream/Downstream Configuration |
| 154 | **/ |
| 155 | typedef enum { |
| 156 | NTB_XLINK_DSD_USP = 2, |
| 157 | NTB_XLINK_USD_DSP |
| 158 | } NTB_XLINK; |
| 159 | |
| 160 | /** |
| 161 | PCIe Link Speed Selection |
| 162 | **/ |
| 163 | typedef enum { |
| 164 | PcieAuto = 0, |
| 165 | PcieGen1, |
| 166 | PcieGen2, |
| 167 | PcieGen3 |
| 168 | } PCIE_LINK_SPEED; |
| 169 | |
| 170 | /** |
| 171 | GPIO Pad Number |
| 172 | **/ |
| 173 | |
| 174 | typedef UINT32 UPD_GPIO_PAD; |
| 175 | |
| 176 | /** |
| 177 | UPD_GPIO_CONFIG: |
| 178 | 64 bit struct defining GPIO PAD configuration |
| 179 | **/ |
| 180 | typedef struct { |
| 181 | /** |
| 182 | Pad Mode |
| 183 | Pad can be set as GPIO or one of its native functions. |
| 184 | When in native mode setting Direction (except Inversion), OutputState, |
| 185 | InterruptConfig and Host Software Pad Ownership are unnecessary. |
| 186 | Refer to definition of GPIO_PAD_MODE. |
| 187 | Refer to EDS for each native mode according to the pad. |
| 188 | **/ |
| 189 | UINT32 PadMode : 4; |
| 190 | /** |
| 191 | Host Software Pad Ownership |
| 192 | Set pad to ACPI mode or GPIO Driver Mode. |
| 193 | Refer to definition of GPIO_HOSTSW_OWN. |
| 194 | **/ |
| 195 | UINT32 HostSoftPadOwn : 2; |
| 196 | /** |
| 197 | GPIO Direction |
| 198 | Can choose between In, In with inversion Out, both In and Out, |
| 199 | both In with inversion and out or disabling both. |
| 200 | Refer to definition of GPIO_DIRECTION for supported settings. |
| 201 | **/ |
| 202 | UINT32 Direction : 5; |
| 203 | /** |
| 204 | Output State |
| 205 | Set Pad output value. |
| 206 | Refer to definition of GPIO_OUTPUT_STATE for supported settings. |
| 207 | This setting takes place when output is enabled. |
| 208 | **/ |
| 209 | UINT32 OutputState : 2; |
| 210 | /** |
| 211 | GPIO Interrupt Configuration |
| 212 | Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting |
| 213 | is applicable only if GPIO is in input mode. |
| 214 | If GPIO is set to cause an SCI then also Gpe is enabled for this pad. |
| 215 | Refer to definition of GPIO_INT_CONFIG for supported settings. |
| 216 | **/ |
| 217 | UINT32 InterruptConfig : 8; |
| 218 | /** |
| 219 | GPIO Power Configuration. |
| 220 | This setting controls Pad Reset Configuration. |
| 221 | Refer to definition of GPIO_RESET_CONFIG for supported settings. |
| 222 | **/ |
| 223 | UINT32 PowerConfig : 4; |
| 224 | |
| 225 | /** |
| 226 | GPIO Electrical Configuration |
| 227 | This setting controls pads termination and voltage tolerance. |
| 228 | Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. |
| 229 | **/ |
| 230 | UINT32 ElectricalConfig : 7; |
| 231 | |
| 232 | /** |
| 233 | GPIO Lock Configuration |
| 234 | This setting controls pads lock. |
| 235 | Refer to definition of GPIO_LOCK_CONFIG for supported settings. |
| 236 | **/ |
| 237 | UINT32 LockConfig : 3; |
| 238 | /** |
| 239 | Additional GPIO configuration |
| 240 | Refer to definition of GPIO_OTHER_CONFIG for supported settings. |
| 241 | **/ |
| 242 | UINT32 OtherSettings : 2; |
| 243 | |
| 244 | UINT32 RsvdBits : 27; ///< Reserved bits for future extension |
| 245 | |
| 246 | UINT32 RsvdBits1; ///< Reserved bits for future extension |
| 247 | } UPD_GPIO_CONFIG; |
| 248 | |
| 249 | /** |
| 250 | UPD_GPIO_INIT_CONFIG: |
| 251 | Defines a GPIO Pad and its respective configuration |
| 252 | Constitutes one entry in the GPIO config table |
| 253 | Reference FSP implementation: |
| 254 | AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\GpioTable.c |
| 255 | Bootloaders can include the following to define GPIO PADs/other macros: |
| 256 | PurleySktPkg\SouthClusterLbg\Include\Library\GpioLib.h |
| 257 | **/ |
| 258 | typedef struct { |
| 259 | UPD_GPIO_PAD GpioPad; |
| 260 | UPD_GPIO_CONFIG GpioConfig; |
| 261 | } UPD_GPIO_INIT_CONFIG; |
| 262 | |
| 263 | /** |
| 264 | GPIOTABLE_CONFIG: |
| 265 | GpioTable - Base Address of the Gpio Table declared by the |
| 266 | bootloader. |
| 267 | Default: NULL |
| 268 | NumberofEntries - Number of Entries in the GPIO Table provided |
| 269 | Default: 0 |
| 270 | If GpioTable is Null or NumberofEntries is 0, then FSP will handle Gpio Pad |
| 271 | configuration using default GPIO_INIT_CONFIG tables |
| 272 | **/ |
| 273 | typedef struct { |
| 274 | UPD_GPIO_INIT_CONFIG *GpioTable; |
| 275 | UINT32 NumberOfEntries; |
| 276 | } GPIOTABLE_CONFIG; |
| 277 | |
| 278 | /** |
| 279 | UPD_IIO_BIFURCATION_DATA_ENTRY: |
| 280 | Defines IIO Bifurcation for IIO Units |
| 281 | Constitutes one entry in the IIO Bifurcation table, describing bifurcation entries as: |
| 282 | Socket | IOU | Bifurcation |
| 283 | Valid IouNumbers are from 0 to 4 |
| 284 | Reference FSP Implementation : |
| 285 | AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\IioBifurInit.c |
| 286 | Definitions for relevant bifurcation macros: |
| 287 | NumberCpRcPkg\Library\BaseMemoryCoreLib\Chip\Skx\Include\Iio\IioRegs.h |
| 288 | **/ |
| 289 | typedef struct { |
| 290 | UINT8 Socket; |
| 291 | UINT8 IouNumber; |
| 292 | UINT8 Bifurcation; |
| 293 | } UPD_IIO_BIFURCATION_DATA_ENTRY; |
| 294 | |
| 295 | /** |
| 296 | IIOBIFURCATION_CONFIG: |
| 297 | IIoBifurcationTable - Base Address of the IIO Bifurcation table |
| 298 | declared by the bootloader |
| 299 | Default: NULL |
| 300 | NumberofEntries - Number of Entries in the IIO Bifurcation Table |
| 301 | Default: 0 |
| 302 | If IIoBifurcationTable is Null or NumberofEntries is 0, then FSP will handle IIO |
| 303 | bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables |
| 304 | **/ |
| 305 | typedef struct { |
| 306 | UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; |
| 307 | UINT32 NumberOfEntries; |
| 308 | } IIOBIFURCATION_CONFIG; |
| 309 | |
| 310 | /** |
| 311 | VTD_CONFIG : |
| 312 | VT direct IO Configuration Support |
| 313 | VTdSupport - Enable/Disable VTd Support |
| 314 | CoherencySupport - Enable/Disable Coherency Support |
| 315 | ATS - Enable/Disable Address Translation Services |
| 316 | FSP Will Disable VTd by default |
| 317 | **/ |
| 318 | typedef struct { |
| 319 | UINT8 VTdSupport; |
| 320 | UINT8 CoherencySupport; |
| 321 | UINT8 ATS; |
| 322 | } VTD_CONFIG; |
| 323 | |
| 324 | /** |
| 325 | UPD_PCIE_PORT_CONFIG |
| 326 | PCIe port configuration |
| 327 | PortIndex - Index of the port to be configured as defined by PCI_PORTS |
| 328 | HidePort - Hide the selected port |
| 329 | DeEmphasis - DeEmphasis of the selected PCIe port |
| 330 | PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set |
| 331 | DfxDnTxPreset - PCIe Downstream Tx Preset, valid values (0x00 - 0x09, |
| 332 | 0xFF is Auto, Auto sets 0x07) |
| 333 | DfxRxPreset - PCIe Downstream Rx Preset, valid values (0x00 - 0x06, 0xFF is Auto) |
| 334 | DfxUpTxPreset - PCIe Upstream Tx Preset, valid values (0x00 - 0x09, 0xFF is Auto) |
| 335 | Sris - Enable/Disable SRIS (0x00 - Disable, 0x01 - Enable) |
| 336 | PcieCommonClock - Configure port clocking. (0x00 - Distinct, 0x01 - Common) |
| 337 | MaxPayload - PCIe Max Payload Size on the port |
| 338 | NtbPpd - NTB port Configuration as defined in NTB_PPD |
| 339 | NtbSplitBar - 0: Use one 64, 1: Use two 32-bit split bars |
| 340 | NtbSBar01Prefetch - Configure Split BAR 0/1 as prefetchable |
| 341 | NtbXlinkCtlOverride - NTB Cross-link as defined in NTB_XLINK |
| 342 | NtbBarSizePBar4 - Set Prefetchable BAR 4 size for the primary NTB side in case |
| 343 | Split Bar is Enabled |
| 344 | NtbBarSizePBar5 - Set Prefetchable BAR 5 size for the primary NTB side in case |
| 345 | Split Bar is Enabled |
| 346 | FSP_WA: Till FSP fixes NtbBarSizeOverride, parameters below are MANDATORY!: |
| 347 | These BAR size registers are write once registers and will be programmed with 0 |
| 348 | if not passed as FSP is |
| 349 | hardcoding NtbBarSizeOverride to 0x01 for now. |
| 350 | Split BAR sizes would need to be programmed mandatorily as well in case split bars |
| 351 | are enabled. |
| 352 | NtbBarSizePBar23 - Set Prefetchable BAR 23 size for the primary NTB side |
| 353 | NtbBarSizePBar45 - Used to set bar 4 and 5 sizes in case Split Bar is Disabled |
| 354 | NtbBarSizeSBar23 - Set Prefetchable BAR 23 size for the secondary NTB side |
| 355 | NtbBarSizeSBar45 - Set Prefetchable BAR 45 size for the secondary NTB side in case |
| 356 | Split Bar is disabled |
| 357 | **/ |
| 358 | typedef struct { |
| 359 | UINT32 PortIndex; |
| 360 | UINT8 HidePort; |
| 361 | UINT8 DeEmphasis; |
| 362 | UINT8 PortLinkSpeed; |
| 363 | UINT8 MaxPayload; |
| 364 | UINT8 DfxDnTxPreset; |
| 365 | UINT8 DfxRxPreset; |
| 366 | UINT8 DfxUpTxPreset; |
| 367 | UINT8 Sris; |
| 368 | UINT8 PcieCommonClock; |
| 369 | UINT8 NtbPpd; |
| 370 | UINT8 NtbSplitBar; |
| 371 | UINT8 NtbBarSizePBar23; |
| 372 | UINT8 NtbBarSizePBar4; |
| 373 | UINT8 NtbBarSizePBar5; |
| 374 | UINT8 NtbBarSizePBar45; |
| 375 | UINT8 NtbBarSizeSBar23; |
| 376 | UINT8 NtbBarSizeSBar4; |
| 377 | UINT8 NtbBarSizeSBar5; |
| 378 | UINT8 NtbBarSizeSBar45; |
| 379 | UINT8 NtbSBar01Prefetch; |
| 380 | UINT8 NtbXlinkCtlOverride; |
| 381 | } UPD_PCI_PORT_CONFIG; |
| 382 | |
| 383 | /** |
| 384 | PCIEPORT_CONFIG: |
| 385 | PciePortConfiguration - Pointer to an array of PCIe port configuration structures |
| 386 | as declared above |
| 387 | NumberOfEntries - Number of elements in the PciePortConfiguration Array |
| 388 | **/ |
| 389 | typedef struct { |
| 390 | UPD_PCI_PORT_CONFIG *ConfigurationTable; |
| 391 | |
| 392 | UINT16 NumberOfEntries; |
| 393 | } IIOPCIPORT_CONFIG; |
| 394 | |
| 395 | /** |
| 396 | UPD_IIO_STACK_RESOURCE_CONFIG: |
| 397 | StackIndex - Index of the CPU IIO Stack to be configured as defined by IIO_STACKS |
| 398 | PciResourceIoBase |
| 399 | PciResourceIoLimit |
| 400 | PciResourceMem32Base |
| 401 | PciResourceMem32Limit |
| 402 | PciResourceMem64Base |
| 403 | PciResourceMem64Limit |
| 404 | **/ |
| 405 | typedef struct { |
| 406 | UINT8 StackIndex; |
| 407 | UINT16 PciResourceIoBase; |
| 408 | UINT16 PciResourceIoLimit; |
| 409 | UINT32 PciResourceMem32Base; |
| 410 | UINT32 PciResourceMem32Limit; |
| 411 | UINT64 PciResourceMem64Base; |
| 412 | UINT64 PciResourceMem64Limit; |
| 413 | } UPD_IIO_STACK_RESOURCE_CONFIG; |
| 414 | |
| 415 | /** |
| 416 | IIORESOURCE_CONFIG: |
| 417 | ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array |
| 418 | NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array |
| 419 | **/ |
| 420 | typedef struct { |
| 421 | UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; |
| 422 | UINT16 NumberOfEntries; |
| 423 | } IIORESOURCE_CONFIG; |
| 424 | |
| 425 | /** |
| 426 | UPD_PCH_PCIE_PORT: |
| 427 | PortIndex - PCH PCIe Port Index. |
| 428 | Valid Port Numbers are: 0 to 19. |
| 429 | Enable - Enable/Disable PCH PCIe port |
| 430 | PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set |
| 431 | **/ |
| 432 | typedef struct { |
| 433 | UINT8 PortIndex; |
| 434 | UINT8 ForceEnable; |
| 435 | UINT8 PortLinkSpeed; |
| 436 | } UPD_PCH_PCIE_PORT; |
| 437 | |
| 438 | /** |
| 439 | PCHPCIPORT_CONFIG: |
| 440 | PciPortConfig - Pointer to an array of PCH PCI Ports to be configured |
| 441 | RootPortFunctionSwapping - Disable root port swapping based on device |
| 442 | connection status |
| 443 | PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage |
| 444 | The value of this policy is in 1/10th percent units. |
| 445 | Valid spread range: 0-20. Auto: 0xFE (sets it to hardware default) |
| 446 | Completely Disable PCIe PLL SSC: 0xFF |
| 447 | A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% |
| 448 | NumberOfEntries - Number of entries in the PCH PCI Port configuration |
| 449 | **/ |
| 450 | typedef struct { |
| 451 | UPD_PCH_PCIE_PORT *PciPortConfig; |
| 452 | UINT8 RootPortFunctionSwapping; |
| 453 | UINT8 PciePllSsc; |
| 454 | UINT16 NumberOfEntries; |
| 455 | } PCHPCIPORT_CONFIG; |
| 456 | |
| 457 | /** FSP-M Configuration |
| 458 | **/ |
| 459 | typedef struct { |
| 460 | |
| 461 | /** Offset 0x0040 - MRC Debug Print Level |
| 462 | Select the FSP MRC debug message print level. Options are a bitmask, so you can |
| 463 | combine options. BIT0:MIN DEBUG, BIT1:MAX DEBUG, BIT2:TRACE, BIT3:MEM TRAIN, BIT4:TEST, |
| 464 | BIT5:CPGC, BIT6:REG ACCESS |
| 465 | **/ |
| 466 | UINT8 PcdFspMrcDebugPrintErrorLevel; |
| 467 | |
| 468 | /** Offset 0x0041 - KTI Debug Print Level |
| 469 | Select the FSP KTI debug message print level. Options are a bitmask, so you can |
| 470 | combine options. BIT0:ERROR, BIT1:WARNING, BIT2:INFO0, BIT3:INFO1 |
| 471 | **/ |
| 472 | UINT8 PcdFspKtiDebugPrintErrorLevel; |
| 473 | |
| 474 | /** Offset 0x0042 - HSUART Device |
| 475 | Select the PCI High Speed UART Device for Serial Port. |
| 476 | 0:HSUART0, 1:HSUART1, 2:HSUART2 |
| 477 | **/ |
| 478 | UINT8 PcdHsuartDevice; |
| 479 | |
| 480 | /** Offset 0x0043 - Customer Revision |
| 481 | The Customer can set this revision string for their own purpose. |
| 482 | **/ |
| 483 | UINT8 PcdCustomerRevision[32]; |
| 484 | |
| 485 | /** Offset 0x0063 - GpioConfig |
| 486 | GpioConfig Struct. Defaults: GpioTable:NULL, NumberOfEntries:0x00 |
| 487 | **/ |
| 488 | GPIOTABLE_CONFIG GpioConfig; |
| 489 | |
| 490 | /** Offset 0x006B - IioBifurcationConfig |
| 491 | IioBifurcationConfig Table Struct. Defaults: IioBifurcationTable:NULL, |
| 492 | NumberOfEntries:0x00 |
| 493 | **/ |
| 494 | IIOBIFURCATION_CONFIG IioBifurcationConfig; |
| 495 | |
| 496 | /** Offset 0x0073 |
| 497 | **/ |
| 498 | UINT8 UnusedUpdSpace0[16]; |
| 499 | |
| 500 | /** Offset 0x0083 - VTdConfig |
| 501 | VTdConfig Struct. Defaults: All values are set to 0. VTd Disabled. |
| 502 | **/ |
| 503 | VTD_CONFIG VTdConfig; |
| 504 | |
| 505 | UINT8 reserved1[35]; |
| 506 | |
| 507 | /** Offset 0x00A9 - Board ID Number |
| 508 | Select the BoardId based on the target Platform. Default assumes an unknown board. |
| 509 | **/ |
| 510 | UINT8 BoardId; |
| 511 | |
| 512 | UINT8 reserved2[24]; |
| 513 | |
| 514 | /** Offset 0x00C2 **/ |
| 515 | VOID *SetupStructPtr; |
| 516 | |
| 517 | UINT8 reserved3[20]; |
| 518 | |
| 519 | /** Offset 0x00DA - IioPciConfig |
| 520 | IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. |
| 521 | **/ |
| 522 | IIOPCIPORT_CONFIG IioPciConfig; |
| 523 | |
| 524 | /** Offset 0x00E0 - PchPciConfig |
| 525 | PCH Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. |
| 526 | **/ |
| 527 | PCHPCIPORT_CONFIG PchPciConfig; |
| 528 | |
| 529 | /** Offset 0x00E8 - IioResourceConfig |
| 530 | IIO Resource Struct. Defaults: All pointers are NULL. All values are set to zero. |
| 531 | **/ |
| 532 | IIORESOURCE_CONFIG IioResourceConfig; |
| 533 | |
| 534 | UINT8 reserved4[3]; |
| 535 | |
| 536 | /** Offset 0x00F1 - DCI Enable |
| 537 | Enable / Disable DCI |
| 538 | $EN_DIS |
| 539 | **/ |
| 540 | UINT8 PchDciEn; |
| 541 | |
| 542 | /** Offset 0x00F2 - IO Margining Tool (IOMT) Enable |
| 543 | Enable / Disable Io Margining Tool |
| 544 | $EN_DIS |
| 545 | **/ |
| 546 | UINT8 IomtEnable; |
| 547 | |
| 548 | /** Offset 0x00F3 - Hyper Threading (HT) disable |
| 549 | Disable Hyper threading. Disable: 0x01 | Enable: 0x00 | Default - HT enabled |
| 550 | $EN_DIS |
| 551 | **/ |
| 552 | UINT8 HyperThreadingDisable; |
| 553 | |
| 554 | /** Offset 0x00F4 |
| 555 | **/ |
| 556 | UINT8 UnusedUpdSpace1[236]; |
| 557 | |
| 558 | /** Offset 0x01E0 |
| 559 | **/ |
| 560 | UINT8 ReservedMemoryInitUpd[16]; |
Jonathan Zhang | fe17a7d | 2022-08-08 15:38:54 -0700 | [diff] [blame] | 561 | } FSPM_CONFIG; |
Jonathan Zhang | 9ab4dc3 | 2020-02-24 17:39:05 -0800 | [diff] [blame] | 562 | |
| 563 | /** Fsp M UPD Configuration |
| 564 | **/ |
| 565 | typedef struct { |
| 566 | |
| 567 | /** Offset 0x0000 |
| 568 | **/ |
| 569 | FSP_UPD_HEADER FspUpdHeader; |
| 570 | |
| 571 | /** Offset 0x0020 |
| 572 | **/ |
| 573 | FSPM_ARCH_UPD FspmArchUpd; |
| 574 | |
| 575 | /** Offset 0x0040 |
| 576 | **/ |
| 577 | FSP_M_CONFIG FspmConfig; |
| 578 | |
| 579 | /** Offset 0x01F0 - FspmVersion |
| 580 | FSP-M UPD Version Number |
| 581 | **/ |
| 582 | UINT16 FspmUpdVersion; |
| 583 | |
| 584 | /** Offset 0x01F2 |
| 585 | **/ |
| 586 | UINT8 UnusedUpdSpace2[12]; |
| 587 | |
| 588 | /** Offset 0x01FE |
| 589 | **/ |
| 590 | UINT16 UpdTerminator; |
| 591 | } FSPM_UPD; |
| 592 | |
| 593 | #pragma pack() |
| 594 | |
| 595 | #endif |