David Milosevic | ad83eb1 | 2023-11-16 05:11:18 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include "chip.h" |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <arch/mmu.h> |
| 6 | #include <bootmem.h> |
| 7 | #include <cbfs.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device_tree.h> |
| 10 | #include <bootmem.h> |
| 11 | #include <arch/mmu.h> |
| 12 | #include <mainboard/addressmap.h> |
| 13 | #include <stdint.h> |
| 14 | #include <symbols.h> |
| 15 | |
| 16 | static size_t ram_size(void) |
| 17 | { |
| 18 | return (size_t)cbmem_top() - (uintptr_t)_dram; |
| 19 | } |
| 20 | |
| 21 | static void mainboard_init(void *chip_info) |
| 22 | { |
| 23 | mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); |
| 24 | } |
| 25 | |
| 26 | void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) |
| 27 | { |
| 28 | *core_count = 0; |
| 29 | struct device *dev = NULL; |
| 30 | while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) |
| 31 | *core_count += 1; |
| 32 | |
| 33 | *thread_count = 1; |
| 34 | } |
| 35 | |
| 36 | static void qemu_aarch64_init(struct device *dev) |
| 37 | { |
| 38 | struct memory_info *mem_info; |
| 39 | |
| 40 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 41 | if (mem_info == NULL) |
| 42 | return; |
| 43 | |
| 44 | memset(mem_info, 0, sizeof(*mem_info)); |
| 45 | |
| 46 | mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; |
| 47 | mem_info->max_capacity_mib = 0x800000; // Fixed at 8 TiB for qemu-sbsa |
| 48 | mem_info->number_of_devices = mem_info->dimm_cnt = 1; |
| 49 | |
| 50 | mem_info->dimm[0].dimm_size = ram_size() / MiB; |
| 51 | mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; |
| 52 | mem_info->dimm[0].ddr_frequency = 0; |
| 53 | mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; |
| 54 | mem_info->dimm[0].bank_locator = 0; |
| 55 | |
| 56 | mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity |
| 57 | mem_info->dimm[0].vdd_voltage = 0; |
| 58 | mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; |
| 59 | } |
| 60 | |
| 61 | static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, |
| 62 | acpi_rsdp_t *rsdp) |
| 63 | { |
| 64 | printk(BIOS_DEBUG, "ACPI: * DBG2\n"); |
| 65 | return acpi_pl011_write_dbg2_uart(rsdp, current, SBSA_UART_BASE, "\\_SB.COM0"); |
| 66 | } |
| 67 | |
| 68 | |
| 69 | static void mainboard_enable(struct device *dev) |
| 70 | { |
| 71 | dev->ops->init = qemu_aarch64_init; |
| 72 | dev->ops->write_acpi_tables = mb_write_acpi_tables; |
| 73 | } |
| 74 | |
| 75 | |
| 76 | struct chip_operations mainboard_ops = { |
| 77 | .enable_dev = mainboard_enable, |
| 78 | .init = mainboard_init, |
| 79 | }; |
| 80 | |
| 81 | struct chip_operations mainboard_emulation_qemu_sbsa_ops = { }; |
| 82 | |
| 83 | static void qemu_aarch64_domain_read_resources(struct device *dev) |
| 84 | { |
| 85 | struct resource *res; |
| 86 | int index = 0; |
| 87 | |
| 88 | /* Initialize the system-wide I/O space constraints. */ |
| 89 | res = new_resource(dev, index++); |
| 90 | res->limit = 0xffffUL; |
| 91 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; |
| 92 | |
| 93 | /* Initialize the system-wide memory resources constraints. */ |
| 94 | res = new_resource(dev, index++); |
| 95 | res->base = SBSA_PCIE_MMIO_BASE; |
| 96 | res->limit = SBSA_PCIE_MMIO_LIMIT; |
| 97 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; |
| 98 | |
| 99 | res = new_resource(dev, index++); |
| 100 | res->base = SBSA_PCIE_MMIO_HIGH_BASE; |
| 101 | res->limit = SBSA_PCIE_MMIO_HIGH_LIMIT; |
| 102 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; |
| 103 | |
| 104 | mmio_range(dev, index++, SBSA_PCIE_ECAM_BASE, SBSA_PCIE_ECAM_SIZE); |
| 105 | |
| 106 | ram_range(dev, index++, (uintptr_t)_dram, ram_size()); |
| 107 | |
| 108 | mmio_range(dev, index++, SBSA_FLASH_BASE, SBSA_FLASH_SIZE); |
| 109 | reserved_ram_range(dev, index++, SBSA_SECMEM_BASE, SBSA_SECMEM_SIZE); |
| 110 | } |
| 111 | |
| 112 | struct device_operations qemu_aarch64_pci_domain_ops = { |
| 113 | .read_resources = qemu_aarch64_domain_read_resources, |
| 114 | .set_resources = pci_domain_set_resources, |
| 115 | .scan_bus = pci_host_bridge_scan_bus, |
| 116 | }; |
| 117 | |
| 118 | static void qemu_sbsa_fill_cpu_ssdt(const struct device *dev) |
| 119 | { |
| 120 | acpigen_write_processor_device(dev->path.gicc_v3.mpidr); |
| 121 | acpigen_write_processor_device_end(); |
| 122 | } |
| 123 | |
| 124 | struct device_operations qemu_sbsa_cpu_ops = { |
| 125 | .acpi_fill_ssdt = qemu_sbsa_fill_cpu_ssdt, |
| 126 | }; |
| 127 | |
| 128 | DECLARE_REGION(fdt_pointer) |
| 129 | static void qemu_aarch64_scan_bus(struct device *dev) |
| 130 | { |
| 131 | struct bus *bus = alloc_bus(dev); |
| 132 | uintptr_t fdt_blob = *(uintptr_t *)_fdt_pointer; |
| 133 | struct device_tree *tree; |
| 134 | struct device_tree_node *node; |
| 135 | char path[14]; |
| 136 | u16 fdt_cpu_count = 0; |
| 137 | struct mainboard_emulation_qemu_sbsa_config *config = dev->chip_info; |
| 138 | |
| 139 | tree = fdt_unflatten((void *)fdt_blob); |
| 140 | if (tree == NULL) |
| 141 | return; |
| 142 | |
| 143 | snprintf(path, sizeof(path), "/cpus/cpu@%d", fdt_cpu_count); |
| 144 | while ((node = dt_find_node_by_path(tree, path, NULL, NULL, 0)) != NULL) { |
| 145 | struct device_tree_property *prop; |
| 146 | int64_t mpidr = -1; |
| 147 | list_for_each(prop, node->properties, list_node) { |
| 148 | if (!strcmp("reg", prop->prop.name)) { |
| 149 | mpidr = be64toh(*(uint64_t *)prop->prop.data); |
| 150 | break; |
| 151 | } |
| 152 | } |
| 153 | if (mpidr >= 0) { |
| 154 | struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, |
| 155 | .gicc_v3 = { .mpidr = mpidr, |
| 156 | .vgic_mi = config->vgic_maintenance_interrupt, |
| 157 | .pi_gsiv = config->performance_interrupt_gsiv, }, |
| 158 | |
| 159 | }; |
| 160 | struct device *cpu = alloc_dev(bus, &devpath); |
| 161 | assert(cpu); |
| 162 | cpu->ops = &qemu_sbsa_cpu_ops; |
| 163 | } |
| 164 | snprintf(path, sizeof(path), "/cpus/cpu@%d", ++fdt_cpu_count); |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | struct device_operations qemu_aarch64_cpu_ops = { |
| 169 | .scan_bus = qemu_aarch64_scan_bus, |
| 170 | }; |