Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ |
| 21 | #define __SOC_NVIDIA_TEGRA124_CHIP_H__ |
| 22 | #include <arch/cache.h> |
| 23 | #include <soc/addressmap.h> |
| 24 | #include "gpio.h" |
| 25 | |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 26 | #define EFAULT 1 |
| 27 | #define EINVAL 2 |
| 28 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 29 | /* this is a misuse of the device tree. We're going to let it go for now but |
| 30 | * we should at minimum have a struct for the display controller, since |
| 31 | * the chip supports two. |
| 32 | */ |
| 33 | struct soc_nvidia_tegra124_config { |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 34 | u32 xres; |
| 35 | u32 yres; |
| 36 | u32 framebuffer_bits_per_pixel; |
| 37 | u32 color_depth; |
| 38 | u32 panel_bits_per_pixel; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 39 | int cache_policy; |
| 40 | /* there are two. It's not unimaginable that we might someday |
| 41 | * have two of these structs in a single mainboard. |
| 42 | */ |
| 43 | u32 display_controller; |
| 44 | u32 framebuffer_base; |
| 45 | /* Technically, we can compute this. At the same time, some platforms |
| 46 | * might want to specify a specific size for their own reasons. If it is |
| 47 | * zero the soc code will compute it as xres*yres*framebuffer_bits_per_pixel/4 |
| 48 | */ |
| 49 | u32 framebuffer_size; |
| 50 | /* GPIOs -- all, some, or none are used. Unused ones can be ignored |
| 51 | * in devicetree.cb since if they are not set there they default to 0, |
| 52 | * and 0 for a gpio means 'unused GPIO'. |
| 53 | */ |
| 54 | gpio_t backlight_en_gpio; |
| 55 | gpio_t lvds_shutdown_gpio; |
| 56 | gpio_t backlight_vdd_gpio; |
| 57 | gpio_t panel_vdd_gpio; |
| 58 | |
| 59 | /* required info. */ |
| 60 | /* pwm to use to set display contrast */ |
| 61 | int pwm; |
| 62 | /* timings -- five numbers, all relative to the previous |
| 63 | * event, not to absolute time. e.g., vdd_data_delay is the |
| 64 | * delay from vdd on to data, not from power on to data. |
| 65 | * This is stated to be four timings in the |
| 66 | * u-boot docs. In any event, in coreboot, we generally |
| 67 | * only delay long enough to let the panel wake up and then |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 68 | * do the control operations -- meaning, for *coreboot* |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 69 | * we probably only need the vdd_delay, but payloads may |
| 70 | * need the other info. |
| 71 | */ |
| 72 | /* Delay before from power on asserting vdd */ |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 73 | int vdd_delay_ms; |
| 74 | |
Ken Chang | 5a056d3 | 2014-04-22 12:55:00 +0800 | [diff] [blame^] | 75 | /* Delay beween pwm and backlight_en_gpio is asserted */ |
| 76 | int pwm_to_bl_delay_ms; |
| 77 | |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 78 | /* Delay before HPD high */ |
| 79 | int vdd_to_hpd_delay_ms; |
| 80 | |
| 81 | int hpd_unplug_min_us; |
| 82 | int hpd_plug_min_us; |
| 83 | int hpd_irq_min_us; |
| 84 | |
| 85 | int href_to_sync; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 86 | int hsync_width; |
| 87 | int hback_porch; |
| 88 | int hfront_porch; |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 89 | int vref_to_sync; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 90 | int vsync_width; |
| 91 | int vback_porch; |
| 92 | int vfront_porch; |
| 93 | |
| 94 | int pixel_clock; |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 95 | |
| 96 | /* The minimum link configuraton settings */ |
| 97 | u32 lane_count; |
| 98 | u32 enhanced_framing; |
| 99 | u32 link_bw; |
| 100 | u32 drive_current; |
| 101 | u32 preemphasis; |
| 102 | u32 postcursor; |
| 103 | |
| 104 | void *dc_data; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | #endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */ |