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Stefan Reinauereca92fb2006-08-23 14:28:37 +00001/*
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00002 * This file is part of the coreboot project.
Stefan Reinauereca92fb2006-08-23 14:28:37 +00003 *
4 * Copyright (C) 2005 Digital Design Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010018 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauereca92fb2006-08-23 14:28:37 +000019 */
20
Uwe Hermannc70e9fc2010-02-15 23:10:19 +000021/*
22 * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
23 */
24
Stefan Reinauereca92fb2006-08-23 14:28:37 +000025#ifndef __SDRAMMODE_H_DEFINED
26#define __SDRAMMODE_H_DEFINED
27
28// SDRAM Mode Register definitions, per JESD79D
29// These are transmitted via A0-A13
30
31// Burst length
32#define SDRAM_BURST_2 (1<<0)
33#define SDRAM_BURST_4 (2<<0)
34#define SDRAM_BURST_8 (3<<0)
35
36#define SDRAM_BURST_SEQUENTIAL (0<<3)
37#define SDRAM_BURST_INTERLEAVED (1<<3)
38
39#define SDRAM_CAS_2_0 (2<<4)
40#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
41#define SDRAM_CAS_1_5 (5<<4) /* Optional */
42#define SDRAM_CAS_2_5 (6<<4)
43#define SDRAM_CAS_MASK (7<<4)
44
45#define SDRAM_MODE_NORMAL (0 << 7)
46#define SDRAM_MODE_TEST (1 << 7)
47#define SDRAM_MODE_DLL_RESET (2 << 7)
48
49// Extended Mode Register
50
51#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
52#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
53
54#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
55#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
56
57#endif // __SDRAMMODE_H_DEFINED