Aaron Durbin | 27ce094 | 2014-09-11 16:07:02 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cpu.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <gic.h> |
| 24 | #include "gic.h" |
| 25 | |
| 26 | enum { |
| 27 | ENABLE_GRP0 = 0x1 << 0, |
| 28 | ENABLE_GRP1 = 0x1 << 1, |
Joseph Lo | 589e63e | 2015-04-29 17:14:03 +0800 | [diff] [blame^] | 29 | FIQ_BYP_DIS_GRP0 = 0x1 << 5, |
| 30 | IRQ_BYP_DIS_GRP0 = 0x1 << 6, |
| 31 | FIQ_BYP_DIS_GRP1 = 0x1 << 7, |
| 32 | IRQ_BYP_DIS_GRP1 = 0x1 << 8, |
Aaron Durbin | 27ce094 | 2014-09-11 16:07:02 -0500 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | struct gic { |
| 36 | struct gicd_mmio *gicd; |
| 37 | struct gicc_mmio *gicc; |
| 38 | size_t num_interrupts; |
| 39 | unsigned int version; |
| 40 | unsigned int security_extensions; |
| 41 | }; |
| 42 | |
| 43 | static struct gic *gic_get(void) |
| 44 | { |
| 45 | static struct gic gic; |
| 46 | |
| 47 | if (gic.gicd == NULL) { |
| 48 | uint32_t typer; |
| 49 | |
| 50 | gic.gicd = gicd_base(); |
| 51 | gic.gicc = gicc_base(); |
| 52 | typer = read32(&gic.gicd->typer); |
| 53 | gic.num_interrupts = 32 * ((typer & 0x1f) + 1); |
| 54 | gic.security_extensions = !!(typer & (1 << 10)); |
| 55 | gic.version = (read32(&gic.gicd->icpidr2) & 0xf0) >> 4; |
| 56 | |
| 57 | printk(BIOS_DEBUG, "GICv%d - %zu ints %s GICD=%p GICC=%p\n", |
| 58 | gic.version, gic.num_interrupts, |
| 59 | gic.security_extensions ? "SecExtn" : "", |
| 60 | gic.gicd, gic.gicc); |
| 61 | } |
| 62 | |
| 63 | return &gic; |
| 64 | } |
| 65 | |
Furquan Shaikh | 1e2abe0 | 2015-04-13 19:57:54 -0700 | [diff] [blame] | 66 | static inline uint32_t gic_read(uint32_t *base) |
| 67 | { |
| 68 | return read32(base); |
| 69 | } |
| 70 | |
Aaron Durbin | 27ce094 | 2014-09-11 16:07:02 -0500 | [diff] [blame] | 71 | static inline void gic_write(uint32_t *base, uint32_t val) |
| 72 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 73 | write32(base, val); |
Aaron Durbin | 27ce094 | 2014-09-11 16:07:02 -0500 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val) |
| 77 | { |
| 78 | size_t i; |
| 79 | |
| 80 | for (i = 0; i < num_regs; i++) |
| 81 | gic_write(base++, val); |
| 82 | } |
| 83 | |
| 84 | static void gic_write_banked_regs(uint32_t *base, size_t interrupts_per_reg, |
| 85 | uint32_t val) |
| 86 | { |
| 87 | /* 1st 32 interrupts are banked per CPU. */ |
| 88 | gic_write_regs(base, 32 / interrupts_per_reg, val); |
| 89 | } |
| 90 | |
| 91 | void gic_init(void) |
| 92 | { |
| 93 | struct gic *gic; |
| 94 | struct gicd_mmio *gicd; |
| 95 | struct gicc_mmio *gicc; |
| 96 | uint32_t cpu_mask; |
| 97 | |
| 98 | gic = gic_get(); |
| 99 | gicd = gic->gicd; |
| 100 | gicc = gic->gicc; |
| 101 | |
| 102 | /* Enable Group 0 and Group 1 in GICD -- banked regs. */ |
| 103 | gic_write(&gicd->ctlr, ENABLE_GRP0 | ENABLE_GRP1); |
| 104 | |
| 105 | /* Enable Group 0 and Group 1 in GICC and enable all priroity levels. */ |
| 106 | gic_write(&gicc->ctlr, ENABLE_GRP0 | ENABLE_GRP1); |
| 107 | gic_write(&gicc->pmr, 1 << 7); |
| 108 | |
| 109 | cpu_mask = 1 << smp_processor_id(); |
| 110 | cpu_mask |= cpu_mask << 8; |
| 111 | cpu_mask |= cpu_mask << 16; |
| 112 | |
| 113 | /* Only write banked registers for secondary CPUs. */ |
| 114 | if (smp_processor_id()) { |
| 115 | gic_write_banked_regs(&gicd->itargetsr[0], 4, cpu_mask); |
| 116 | /* Put interrupts into Group 1. */ |
| 117 | gic_write_banked_regs(&gicd->igroupr[0], 32, ~0x0); |
| 118 | /* Allow Non-secure access to everything. */ |
| 119 | gic_write_banked_regs(&gicd->nsacr[0], 16, ~0x0); |
| 120 | return; |
| 121 | } |
| 122 | |
| 123 | /* All interrupts routed to processors that execute this function. */ |
| 124 | gic_write_regs(&gicd->itargetsr[0], gic->num_interrupts / 4, cpu_mask); |
| 125 | /* Put all interrupts into Gropup 1. */ |
| 126 | gic_write_regs(&gicd->igroupr[0], gic->num_interrupts / 32, ~0x0); |
| 127 | /* Allow Non-secure access to everything. */ |
| 128 | gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0); |
| 129 | } |
Furquan Shaikh | 1e2abe0 | 2015-04-13 19:57:54 -0700 | [diff] [blame] | 130 | |
| 131 | void gic_disable(void) |
| 132 | { |
| 133 | struct gic *gic; |
| 134 | struct gicc_mmio *gicc; |
| 135 | |
| 136 | gic = gic_get(); |
| 137 | gicc = gic->gicc; |
| 138 | |
| 139 | /* Disable secure, non-secure interrupts. */ |
| 140 | uint32_t val = gic_read(&gicc->ctlr); |
| 141 | val &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
Joseph Lo | 589e63e | 2015-04-29 17:14:03 +0800 | [diff] [blame^] | 142 | /* |
| 143 | * Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs. |
| 144 | * So the CPU can wake up from power gating state when the GIC |
| 145 | * was disabled. |
| 146 | */ |
| 147 | val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 | |
| 148 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; |
Furquan Shaikh | 1e2abe0 | 2015-04-13 19:57:54 -0700 | [diff] [blame] | 149 | gic_write(&gicc->ctlr, val); |
| 150 | } |
| 151 | |
| 152 | void gic_enable(void) |
| 153 | { |
| 154 | struct gic *gic; |
| 155 | struct gicc_mmio *gicc; |
| 156 | |
| 157 | gic = gic_get(); |
| 158 | gicc = gic->gicc; |
| 159 | |
| 160 | /* Enable secure, non-secure interrupts. */ |
| 161 | uint32_t val = gic_read(&gicc->ctlr); |
| 162 | val |= (ENABLE_GRP0 | ENABLE_GRP1); |
| 163 | gic_write(&gicc->ctlr, val); |
| 164 | } |