Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 2 | |
| 3 | #ifndef _CPU_INTEL_MODEL_206AX_H |
| 4 | #define _CPU_INTEL_MODEL_206AX_H |
| 5 | |
Elyes Haouas | ad65e8c | 2022-10-31 14:02:13 +0100 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
Elyes HAOUAS | dfbe6bd | 2018-10-29 06:56:52 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Angel Pons | 47a80a0 | 2020-12-07 13:15:23 +0100 | [diff] [blame] | 9 | /* SandyBridge CPU stepping */ |
Angel Pons | 7e3126d | 2020-12-07 13:17:18 +0100 | [diff] [blame] | 10 | #define SNB_STEP_B2 2 |
| 11 | #define SNB_STEP_C0 3 |
Angel Pons | 47a80a0 | 2020-12-07 13:15:23 +0100 | [diff] [blame] | 12 | #define SNB_STEP_D0 5 /* Also J0 */ |
| 13 | #define SNB_STEP_D1 6 |
| 14 | #define SNB_STEP_D2 7 /* Also J1/Q0 */ |
| 15 | |
| 16 | /* IvyBridge CPU stepping */ |
| 17 | #define IVB_STEP_A0 0 |
| 18 | #define IVB_STEP_B0 2 |
| 19 | #define IVB_STEP_C0 4 |
| 20 | #define IVB_STEP_K0 5 |
| 21 | #define IVB_STEP_D0 6 |
Angel Pons | 7e3126d | 2020-12-07 13:17:18 +0100 | [diff] [blame] | 22 | #define IVB_STEP_E0 8 |
| 23 | #define IVB_STEP_E1 9 |
Angel Pons | 47a80a0 | 2020-12-07 13:15:23 +0100 | [diff] [blame] | 24 | |
| 25 | #define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) |
| 26 | #define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) |
| 27 | #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) |
| 28 | #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) |
| 29 | #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) |
| 30 | |
| 31 | #define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) |
| 32 | #define IS_IVY_CPU_C(x) ((x & 0xf) == 4) |
| 33 | #define IS_IVY_CPU_K(x) ((x & 0xf) == 5) |
| 34 | #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) |
| 35 | #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) |
| 36 | |
Stefan Reinauer | c0f2cfb | 2012-07-10 17:16:10 -0700 | [diff] [blame] | 37 | /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 38 | #define SANDYBRIDGE_BCLK 100 |
| 39 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 40 | #define MSR_CORE_THREAD_COUNT 0x35 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 41 | #define MSR_FEATURE_CONFIG 0x13c |
Duncan Laurie | 22935e1 | 2012-07-09 09:58:35 -0700 | [diff] [blame] | 42 | #define MSR_FLEX_RATIO 0x194 |
| 43 | #define FLEX_RATIO_LOCK (1 << 20) |
| 44 | #define FLEX_RATIO_EN (1 << 16) |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 45 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 46 | #define MSR_LT_LOCK_MEMORY 0x2e7 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 47 | #define MSR_PLATFORM_INFO 0xce |
| 48 | #define PLATFORM_INFO_SET_TDP (1 << 29) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 49 | |
| 50 | #define MSR_MISC_PWR_MGMT 0x1aa |
| 51 | #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) |
| 52 | #define MSR_TURBO_RATIO_LIMIT 0x1ad |
| 53 | #define MSR_POWER_CTL 0x1fc |
| 54 | |
| 55 | #define MSR_PKGC3_IRTL 0x60a |
| 56 | #define MSR_PKGC6_IRTL 0x60b |
| 57 | #define MSR_PKGC7_IRTL 0x60c |
| 58 | #define IRTL_VALID (1 << 15) |
| 59 | #define IRTL_1_NS (0 << 10) |
| 60 | #define IRTL_32_NS (1 << 10) |
| 61 | #define IRTL_1024_NS (2 << 10) |
| 62 | #define IRTL_32768_NS (3 << 10) |
| 63 | #define IRTL_1048576_NS (4 << 10) |
| 64 | #define IRTL_33554432_NS (5 << 10) |
| 65 | #define IRTL_RESPONSE_MASK (0x3ff) |
| 66 | |
| 67 | /* long duration in low dword, short duration in high dword */ |
| 68 | #define MSR_PKG_POWER_LIMIT 0x610 |
| 69 | #define PKG_POWER_LIMIT_MASK 0x7fff |
| 70 | #define PKG_POWER_LIMIT_EN (1 << 15) |
| 71 | #define PKG_POWER_LIMIT_CLAMP (1 << 16) |
| 72 | #define PKG_POWER_LIMIT_TIME_SHIFT 17 |
| 73 | #define PKG_POWER_LIMIT_TIME_MASK 0x7f |
| 74 | |
| 75 | #define MSR_PP0_CURRENT_CONFIG 0x601 |
| 76 | #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ |
| 77 | #define MSR_PP1_CURRENT_CONFIG 0x602 |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 78 | #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ |
| 79 | #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 80 | #define MSR_PKG_POWER_SKU_UNIT 0x606 |
| 81 | #define MSR_PKG_POWER_SKU 0x614 |
| 82 | #define MSR_PP0_POWER_LIMIT 0x638 |
| 83 | #define MSR_PP1_POWER_LIMIT 0x640 |
| 84 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 85 | #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 |
| 86 | #define MSR_CONFIG_TDP_NOMINAL 0x648 |
| 87 | #define MSR_CONFIG_TDP_LEVEL1 0x649 |
| 88 | #define MSR_CONFIG_TDP_LEVEL2 0x64a |
| 89 | #define MSR_CONFIG_TDP_CONTROL 0x64b |
| 90 | #define MSR_TURBO_ACTIVATION_RATIO 0x64c |
| 91 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 92 | /* P-state configuration */ |
| 93 | #define PSS_MAX_ENTRIES 8 |
| 94 | #define PSS_RATIO_STEP 2 |
| 95 | #define PSS_LATENCY_TRANSITION 10 |
| 96 | #define PSS_LATENCY_BUSMASTER 10 |
| 97 | |
Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 98 | /* Sanity check config options. */ |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 99 | #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) |
| 100 | # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" |
Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 101 | #endif |
| 102 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 103 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 104 | #endif |
| 105 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 106 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 107 | #endif |
| 108 | #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) |
| 109 | # error "CONFIG_IED_REGION_SIZE is not a power of 2" |
| 110 | #endif |
| 111 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 112 | /* Lock MSRs */ |
| 113 | void intel_model_206ax_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 114 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 115 | /* Configure power limits for turbo mode */ |
| 116 | void set_power_limits(u8 power_limit_1_time); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 117 | int cpu_config_tdp_levels(void); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 118 | int get_platform_id(void); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 119 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 120 | static inline u8 cpu_stepping(void) |
| 121 | { |
| 122 | return cpuid_eax(1) & 0xf; |
| 123 | } |
| 124 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 125 | #endif |