Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <fsp/api.h> |
| 5 | #include <soc/romstage.h> |
| 6 | #include <soc/meminit.h> |
| 7 | |
| 8 | static const struct mb_cfg ddr5_mem_config = { |
| 9 | .type = MEM_TYPE_DDR5, |
| 10 | |
| 11 | .rcomp = { |
| 12 | /* Baseboard uses only 100ohm Rcomp resistor */ |
| 13 | .resistor = 100, |
| 14 | |
| 15 | /* Baseboard Rcomp target values */ |
| 16 | .targets = { 50, 30, 30, 30, 27 }, |
| 17 | }, |
| 18 | |
| 19 | .ect = true, /* Early Command Training */ |
| 20 | |
| 21 | .UserBd = BOARD_TYPE_MOBILE, |
| 22 | |
| 23 | .LpDdrDqDqsReTraining = 1, |
| 24 | |
| 25 | .ddr_config = { |
| 26 | .dq_pins_interleaved = false, |
| 27 | } |
| 28 | }; |
| 29 | |
Zhuohao Lee | 09f3b6c | 2022-01-20 21:30:12 +0800 | [diff] [blame] | 30 | void mainboard_memory_init_params(FSPM_UPD *memupd) |
Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 31 | { |
Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 32 | const struct mb_cfg *mem_config = &ddr5_mem_config; |
| 33 | const bool half_populated = false; |
| 34 | |
| 35 | const struct mem_spd dimm_module_spd_info = { |
| 36 | .topo = MEM_TOPO_DIMM_MODULE, |
| 37 | .smbus = { |
Maximilian Brune | e01e9b8 | 2022-08-25 14:22:47 +0200 | [diff] [blame] | 38 | [0] = { |
| 39 | .addr_dimm[0] = 0x50, |
| 40 | }, |
| 41 | [1] = { |
Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 42 | .addr_dimm[0] = 0x52, |
Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 43 | }, |
| 44 | }, |
| 45 | }; |
| 46 | |
Subrata Banik | 4703edc | 2022-03-10 19:12:02 +0530 | [diff] [blame] | 47 | memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); |
Lean Sheng Tan | 5a0c10c | 2023-01-23 14:55:28 +0100 | [diff] [blame] | 48 | |
| 49 | /* Enable Audio */ |
| 50 | memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; |
| 51 | memupd->FspmConfig.PchHdaSdiEnable[0] = 1; |
| 52 | memupd->FspmConfig.PchHdaSdiEnable[1] = 1; |
Maximilian Brune | 4f13239 | 2023-02-23 19:07:41 +0100 | [diff] [blame] | 53 | |
| 54 | // CPU rootports do not have a ClockReq connected on Atlas. If this is not done, |
| 55 | // the following will happens: |
| 56 | // - FSP will enable power management for cpu rootport. |
| 57 | // - coreboot enables ASPM on CPU root port on pci enemuration |
| 58 | // - machine exception is thrown, when trying to access pci configuration space after |
| 59 | // enabling ASPM src/device/pciexp_device.c:pciexp_tune_dev(). |
| 60 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; |
| 61 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; |
| 62 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; |
Maximilian Brune | 586b1c8 | 2023-03-22 16:08:13 +0100 | [diff] [blame^] | 63 | |
| 64 | // shared clock |
| 65 | memupd->FspmConfig.PcieClkSrcUsage[0] = 0x80; |
| 66 | memupd->FspmConfig.PcieClkSrcClkReq[0] = 0xFF; |
| 67 | // i225 |
| 68 | memupd->FspmConfig.PcieClkSrcUsage[1] = 9; // RP 10 |
| 69 | memupd->FspmConfig.PcieClkSrcClkReq[1] = 1; |
| 70 | |
| 71 | // FIX Apparently Rootports don't like the idea of not having a clksrc and clkreq |
| 72 | // attached to it. For example if we set PcieClkSrcClkReq[1] above to 0xFF (unused) |
| 73 | // it will not come back out of L1. You can easily test this on windows by trying to |
| 74 | // update the i225 driver in device manager or use setpci in Linux to set Device in D3. |
| 75 | // The same applies to all other rootports no matter which devices are connected to it. |
| 76 | // Therefore we put each rootport (that does not have a clkreq, clksrc) |
| 77 | // to a not connected (not routed out) clksrc and clkreq. That seems to be a current FSP Bug. |
| 78 | // workaround and will be removed as soon as FSP is fixed. |
| 79 | memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // Rootport 5 |
| 80 | memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; |
| 81 | memupd->FspmConfig.PcieClkSrcUsage[3] = 5; // Rootport 6 |
| 82 | memupd->FspmConfig.PcieClkSrcClkReq[3] = 0; |
| 83 | memupd->FspmConfig.PcieClkSrcUsage[4] = 8; // Rootport 9 |
| 84 | memupd->FspmConfig.PcieClkSrcClkReq[4] = 0; |
| 85 | memupd->FspmConfig.PcieClkSrcUsage[5] = 6; // Rootport 7 |
| 86 | memupd->FspmConfig.PcieClkSrcClkReq[5] = 0; |
| 87 | memupd->FspmConfig.PcieClkSrcUsage[6] = 7; // Rootport 8 |
| 88 | memupd->FspmConfig.PcieClkSrcClkReq[6] = 0; |
Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 89 | } |