Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_BLOCK_PMC |
| 2 | depends on SOC_INTEL_COMMON_BLOCK_GPIO |
Shaunak Saha | 07f5b62 | 2017-08-11 12:33:20 -0700 | [diff] [blame] | 3 | depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 4 | bool |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 5 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 6 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 7 | help |
| 8 | Intel Processor common code for Power Management controller(PMC) |
| 9 | subsystem |
Subrata Banik | 9b98feb | 2017-12-13 11:02:43 +0530 | [diff] [blame] | 10 | |
Tim Chu | adb6922 | 2020-07-09 18:30:56 -0700 | [diff] [blame] | 11 | if SOC_INTEL_COMMON_BLOCK_PMC |
| 12 | |
| 13 | config POWER_STATE_DEFAULT_ON_AFTER_FAILURE |
| 14 | default y |
| 15 | |
Arthur Heymans | 1ae8cd1 | 2020-11-19 13:59:53 +0100 | [diff] [blame] | 16 | config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
| 17 | bool |
| 18 | help |
| 19 | Select this on platforms where the PMC device is discoverable |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 20 | when scanning buses. |
Arthur Heymans | 1ae8cd1 | 2020-11-19 13:59:53 +0100 | [diff] [blame] | 21 | |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 22 | config SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Lean Sheng Tan | 508dc16 | 2021-06-16 01:32:22 -0700 | [diff] [blame] | 23 | bool |
| 24 | help |
| 25 | Enable this for PMC devices to perform EPOC (CPU Early Power-on |
| 26 | Configuration) related functions. |
| 27 | |
Tim Chu | adb6922 | 2020-07-09 18:30:56 -0700 | [diff] [blame] | 28 | endif # SOC_INTEL_COMMON_BLOCK_PMC |
| 29 | |
Hannah Williams | 1177bf5 | 2017-12-13 12:44:26 -0800 | [diff] [blame] | 30 | config PMC_INVALID_READ_AFTER_WRITE |
| 31 | bool |
| 32 | default n |
| 33 | help |
| 34 | Enable this for PMC devices where a read back of ACPI BAR and |
| 35 | IO access bit does not return the previously written value. |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 36 | |
Duncan Laurie | 44caa19 | 2020-10-10 00:05:36 +0000 | [diff] [blame] | 37 | config PMC_IPC_ACPI_INTERFACE |
| 38 | bool |
| 39 | default n |
| 40 | depends on HAVE_ACPI_TABLES |
| 41 | help |
| 42 | Enable this to have the PMC IPC mailbox ACPI interface added |
| 43 | to the SSDT for use by other drivers. |
| 44 | |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 45 | config PMC_GLOBAL_RESET_ENABLE_LOCK |
| 46 | bool |
| 47 | help |
| 48 | Enable this for PMC devices where the reset configuration |
| 49 | and lock register is located under PMC BASE at offset ETR. |
| 50 | Note that the reset register is still at 0xCF9 this only |
| 51 | controls the enable and lock feature. |
Subrata Banik | 3e959d8 | 2020-09-28 17:50:00 +0530 | [diff] [blame] | 52 | |
Michael Niewöhner | c9a12f2 | 2021-09-24 23:22:51 +0200 | [diff] [blame] | 53 | config NO_PM_ACPI_TIMER |
| 54 | bool |
| 55 | help |
| 56 | Selected by SoCs that do not have a PM ACPI timer. |
| 57 | |
Michael Niewöhner | 5df952b | 2020-10-02 17:57:47 +0200 | [diff] [blame] | 58 | config USE_PM_ACPI_TIMER |
| 59 | bool "Enable ACPI PM timer" |
| 60 | default y |
Michael Niewöhner | c9a12f2 | 2021-09-24 23:22:51 +0200 | [diff] [blame] | 61 | depends on !NO_PM_ACPI_TIMER |
Michael Niewöhner | 5df952b | 2020-10-02 17:57:47 +0200 | [diff] [blame] | 62 | help |
| 63 | This should be disabled for devices running on battery since |
| 64 | it can draw much power. Further, it must be disabled, if S0ix |
| 65 | is enabled. |
| 66 | |
| 67 | Disabling this option also stops the hardware TCO timer and makes |
| 68 | the TCO watchdog unavailable. |
| 69 | |
Michael Niewöhner | c47fc40 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 70 | Note: On platforms without uCode PM Timer emulation, legacy OSes |
| 71 | or payloads with ACPI version < 5.0A might not work without |
| 72 | PM ACPI timer. |
| 73 | |
| 74 | (Legacy) software requiring `TMR_STS` (for timer overflow |
| 75 | interrupts) will not work with this option disabled. |