Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_APOLLOLAKE_CHIP_H_ |
| 4 | #define _SOC_APOLLOLAKE_CHIP_H_ |
| 5 | |
Pratik Prajapati | ff3162b | 2017-12-07 10:46:09 -0800 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 7 | #include <drivers/intel/gma/gma.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 9 | #include <intelblocks/gspi.h> |
Furquan Shaikh | 6e37e90 | 2016-07-28 13:44:53 -0700 | [diff] [blame] | 10 | #include <soc/gpe.h> |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 11 | #include <soc/gpio.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 12 | #include <intelblocks/lpc_lib.h> |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 13 | #include <intelblocks/power_limit.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 14 | #include <device/i2c_simple.h> |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 15 | #include <drivers/i2c/designware/dw_i2c.h> |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 16 | #include <soc/pm.h> |
Kane Chen | 9d490da | 2017-01-11 12:53:58 +0800 | [diff] [blame] | 17 | #include <soc/usb.h> |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 18 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 19 | #define MAX_PCIE_PORTS 6 |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #define CLKREQ_DISABLED 0xf |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 21 | |
Divya Chellap | 0b15b70 | 2017-11-29 18:53:03 +0530 | [diff] [blame] | 22 | enum pnp_settings { |
| 23 | PNP_PERF, |
| 24 | PNP_POWER, |
| 25 | PNP_PERF_POWER, |
| 26 | }; |
| 27 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 28 | struct soc_intel_apollolake_config { |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 29 | |
| 30 | /* Common structure containing soc config data required by common code*/ |
| 31 | struct soc_intel_common_config common_soc_config; |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 32 | |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 33 | /* Common struct containing power limits configuration info */ |
| 34 | struct soc_power_limits_config power_limits_config; |
| 35 | |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 36 | /* |
| 37 | * IGD panel configuration |
| 38 | * |
| 39 | * Second backlight control shares logic with other pins (aka. display utility pin). |
| 40 | * Be sure it's used for PWM before setting any secondary backlight value. |
| 41 | */ |
| 42 | struct i915_gpu_panel_config panel_cfg[2]; |
Nico Huber | 2a16331 | 2020-01-06 17:42:45 +0100 | [diff] [blame] | 43 | |
Matt DeVillier | d7ef450 | 2020-04-21 01:23:10 -0500 | [diff] [blame] | 44 | /* i915 struct for GMA backlight control */ |
| 45 | struct i915_gpu_controller_info gfx; |
| 46 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 47 | /* |
| 48 | * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has |
| 49 | * four CLKREQ inputs, but six root ports. Root ports without an |
| 50 | * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" |
| 51 | */ |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 52 | uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; |
Alexandru Gagniuc | 3aa34a8 | 2016-04-04 10:47:49 -0700 | [diff] [blame] | 53 | |
Furquan Shaikh | 2cfc862 | 2018-03-14 21:43:04 -0700 | [diff] [blame] | 54 | /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */ |
| 55 | uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; |
| 56 | |
Shamile Khan | c4276a3 | 2018-03-14 18:09:19 -0700 | [diff] [blame] | 57 | /* De-emphasis enable configuration for each PCIe root port */ |
| 58 | uint8_t pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; |
| 59 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 60 | /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. |
| 61 | * [6:0] SDR mode Number of dealy elements.Each = 125pSec. |
| 62 | */ |
| 63 | uint32_t emmc_tx_cmd_cntl; |
| 64 | |
| 65 | /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. |
| 66 | * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. |
| 67 | */ |
| 68 | uint32_t emmc_tx_data_cntl1; |
| 69 | |
| 70 | /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. |
| 71 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. |
| 72 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 73 | * [6:0] SDR12/Compatibility mode Number of dealy elements. |
| 74 | * Each = 125pSec. |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 75 | */ |
| 76 | uint32_t emmc_tx_data_cntl2; |
| 77 | |
| 78 | /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. |
| 79 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. |
| 80 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 81 | * [6:0] SDR12/Compatibility mode Number of dealy elements. |
| 82 | * Each = 125pSec. |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 83 | */ |
| 84 | uint32_t emmc_rx_cmd_data_cntl1; |
| 85 | |
| 86 | /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. |
| 87 | * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. |
| 88 | */ |
| 89 | uint32_t emmc_rx_strobe_cntl; |
| 90 | |
| 91 | /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. |
| 92 | * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. |
| 93 | */ |
| 94 | uint32_t emmc_rx_cmd_data_cntl2; |
| 95 | |
Mario Scheithauer | 9116eb6 | 2018-08-23 11:39:19 +0200 | [diff] [blame] | 96 | /* Select the eMMC max speed allowed. */ |
| 97 | uint8_t emmc_host_max_speed; |
| 98 | |
Sean Rhodes | de198bb | 2022-05-19 15:34:35 +0100 | [diff] [blame] | 99 | /* Sata Ports Hot Plug */ |
| 100 | uint8_t SataPortsHotPlug[2]; |
| 101 | |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame^] | 102 | /* Sata Ports Enable */ |
| 103 | uint8_t SataPortsEnable[2]; |
| 104 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 105 | /* Specifies on which IRQ the SCI will internally appear. */ |
| 106 | uint8_t sci_irq; |
| 107 | |
Alexandru Gagniuc | 3aa34a8 | 2016-04-04 10:47:49 -0700 | [diff] [blame] | 108 | /* Configure serial IRQ (SERIRQ) line. */ |
| 109 | enum serirq_mode serirq_mode; |
Hannah Williams | 483004f | 2016-03-28 14:45:59 -0700 | [diff] [blame] | 110 | |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 111 | uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 112 | uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 113 | uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 114 | |
Sean Rhodes | 2d58d5c | 2022-01-19 08:13:38 +0000 | [diff] [blame] | 115 | /* LPC fixed enables and ranges */ |
| 116 | uint16_t lpc_iod; |
| 117 | uint16_t lpc_ioe; |
| 118 | |
Sean Rhodes | 7a82a80 | 2022-06-02 11:28:43 +0100 | [diff] [blame] | 119 | /* Generic IO decode ranges */ |
| 120 | uint32_t gen1_dec; |
| 121 | uint32_t gen2_dec; |
| 122 | uint32_t gen3_dec; |
| 123 | uint32_t gen4_dec; |
| 124 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 125 | /* Configure LPSS S0ix Enable */ |
| 126 | uint8_t lpss_s0ix_enable; |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 127 | |
| 128 | /* Enable DPTF support */ |
| 129 | int dptf_enable; |
Aaron Durbin | 41a3fa6 | 2016-08-25 15:42:04 -0500 | [diff] [blame] | 130 | |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 131 | /* TCC activation offset value in degrees Celsius */ |
Angel Pons | 643c82e | 2020-09-24 16:43:21 +0200 | [diff] [blame] | 132 | uint32_t tcc_offset; |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 133 | |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 134 | /* Configure Audio clk gate and power gate |
| 135 | * IOSF-SB port ID 92 offset 0x530 [5] and [3] |
| 136 | */ |
| 137 | uint8_t hdaudio_clk_gate_enable; |
| 138 | uint8_t hdaudio_pwr_gate_enable; |
| 139 | uint8_t hdaudio_bios_config_lockdown; |
| 140 | |
Sean Rhodes | 9d894b8 | 2022-05-26 22:20:41 +0100 | [diff] [blame] | 141 | /* Enhanced C-states */ |
| 142 | int enhanced_cstates; |
| 143 | |
Aaron Durbin | 41a3fa6 | 2016-08-25 15:42:04 -0500 | [diff] [blame] | 144 | /* SLP S3 minimum assertion width. */ |
| 145 | int slp_s3_assertion_width_usecs; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 146 | |
| 147 | /* GPIO pin for PERST_0 */ |
| 148 | uint16_t prt0_gpio; |
Kane Chen | 9d490da | 2017-01-11 12:53:58 +0800 | [diff] [blame] | 149 | |
| 150 | /* USB2 eye diagram settings per port */ |
| 151 | struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; |
| 152 | |
Maxim Polyakov | 6704049 | 2020-02-16 11:51:57 +0300 | [diff] [blame] | 153 | /* Override USB port configuration */ |
| 154 | uint8_t usb_config_override; |
| 155 | struct usb_port_config usb2_port[APOLLOLAKE_USB2_PORT_MAX]; |
| 156 | struct usb_port_config usb3_port[APOLLOLAKE_USB3_PORT_MAX]; |
| 157 | |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 158 | /* GPIO SD card detect pin */ |
| 159 | unsigned int sdcard_cd_gpio; |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 160 | |
Divya Chellap | 0b15b70 | 2017-11-29 18:53:03 +0530 | [diff] [blame] | 161 | /* Select PNP Settings. |
| 162 | * (0) Performance, |
| 163 | * (1) Power |
| 164 | * (2) Power & Performance */ |
| 165 | enum pnp_settings pnp_settings; |
John Zhao | e673e5c | 2018-10-30 15:12:11 -0700 | [diff] [blame] | 166 | |
| 167 | /* PMIC PCH_PWROK delay configuration - IPC Configuration |
| 168 | * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address |
| 169 | * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) |
| 170 | */ |
| 171 | uint32_t PmicPmcIpcCtrl; |
John Zhao | 91600a3 | 2019-01-10 12:13:38 -0800 | [diff] [blame] | 172 | |
| 173 | /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not |
| 174 | * disable Compliance Mode. Set TRUE to disable Compliance Mode. |
| 175 | * 0:FALSE(Default), 1:True. |
| 176 | */ |
| 177 | uint8_t DisableComplianceMode; |
John Zhao | 9a4beb4 | 2019-01-28 16:04:35 -0800 | [diff] [blame] | 178 | |
| 179 | /* Options to change USB3 ModPhy setting for the Integrated Filter (IF) |
| 180 | * value. Default is 0 to not changing default IF value (0x12). Set |
| 181 | * value with the range from 0x01 to 0xff to change IF value. |
| 182 | */ |
| 183 | uint8_t ModPhyIfValue; |
| 184 | |
| 185 | /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing |
| 186 | * LDO voltage. Set TRUE to increase LDO voltage with 40mV. |
| 187 | * 0:FALSE (default), 1:True. |
| 188 | */ |
| 189 | uint8_t ModPhyVoltageBump; |
| 190 | |
| 191 | /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting |
| 192 | * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage |
| 193 | * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) |
| 194 | * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: |
| 195 | * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). |
| 196 | */ |
| 197 | uint32_t PmicVdd2Voltage; |
Werner Zeh | 279afdc | 2019-02-01 12:32:51 +0100 | [diff] [blame] | 198 | |
| 199 | /* Option to enable VTD feature. Default is 0 which disables VTD |
| 200 | * capability in FSP. Setting this option to 1 in devicetree will enable |
| 201 | * the Upd parameter VtdEnable. |
| 202 | */ |
| 203 | uint8_t enable_vtd; |
Marx Wang | abc17d1 | 2020-04-07 16:58:38 +0800 | [diff] [blame] | 204 | |
| 205 | /* Options to disable the LFPS periodic sampling for USB3 Ports. |
| 206 | * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic sampling |
| 207 | * interval is 9ms. |
| 208 | * Set 1 to update XHCI host MMIO BAR + PMCTRL_REG (0x80A4 bits[7:4]) to 0 |
| 209 | * 0:Enable (default), 1:Disable. |
| 210 | */ |
| 211 | uint8_t disable_xhci_lfps_pm; |
Mario Scheithauer | b11f381 | 2022-01-26 11:49:10 +0100 | [diff] [blame] | 212 | |
| 213 | /* SATA Aggressive Link Power Management */ |
| 214 | uint8_t DisableSataSalpSupport; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 215 | }; |
| 216 | |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 217 | typedef struct soc_intel_apollolake_config config_t; |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 218 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 219 | #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |