| zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 18 | # |
| 19 | |
| 20 | config CPU_AMD_AGESA_FAMILY15_TN |
| 21 | bool |
| 22 | select PCI_IO_CFG_EXT |
| Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 23 | select X86_AMD_FIXED_MTRRS |
| zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 24 | |
| 25 | config CPU_ADDR_BITS |
| 26 | int |
| Zheng Bao | 105da50 | 2013-01-05 12:17:46 +0800 | [diff] [blame] | 27 | default 48 |
| zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 28 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 29 | |
| 30 | config CPU_SOCKET_TYPE |
| 31 | hex |
| 32 | default 0x10 |
| 33 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 34 | |
| 35 | # DDR2 and REG |
| 36 | config DIMM_SUPPORT |
| 37 | hex |
| 38 | default 0x0104 |
| 39 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 40 | |
| 41 | config EXT_RT_TBL_SUPPORT |
| 42 | bool |
| 43 | default n |
| 44 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 45 | |
| 46 | config EXT_CONF_SUPPORT |
| 47 | bool |
| 48 | default n |
| 49 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 50 | |
| 51 | config CBB |
| 52 | hex |
| 53 | default 0x0 |
| 54 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 55 | |
| 56 | config CDB |
| 57 | hex |
| 58 | default 0x18 |
| 59 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 60 | |
| 61 | config XIP_ROM_BASE |
| 62 | hex |
| 63 | default 0xfff80000 |
| 64 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 65 | |
| 66 | config XIP_ROM_SIZE |
| 67 | hex |
| 68 | default 0x100000 |
| 69 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 70 | |
| 71 | config HAVE_INIT_TIMER |
| 72 | bool |
| 73 | default y |
| 74 | depends on CPU_AMD_AGESA_FAMILY15_TN |
| 75 | |
| 76 | config HIGH_SCRATCH_MEMORY_SIZE |
| 77 | hex |
| 78 | # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) |
| 79 | default 0xA1000 |
| 80 | depends on CPU_AMD_AGESA_FAMILY15_TN |