| Angel Pons | 567ece4 | 2022-05-06 21:56:48 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <southbridge/intel/lynxpoint/pch.h> |
| 6 | #include <types.h> |
| 7 | |
| 8 | void pch_dmi_setup_physical_layer(void) |
| 9 | { |
| 10 | /** FIXME: We need to make sure the SA supports Gen2 as well **/ |
| 11 | if ((RCBA32(0x21a4) & 0x0f) == 0x02) { |
| 12 | /* Set Gen 2 Common Clock N_FTS */ |
| 13 | RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16); |
| 14 | |
| 15 | /* Set Target Link Speed to DMI Gen2 */ |
| 16 | RCBA8_AND_OR(DLCTL2, ~0x07, 0x02); |
| 17 | } |
| 18 | } |
| 19 | |
| 20 | #define VC_ACTIVE (1U << 31) |
| 21 | |
| 22 | #define VCNEGPND (1 << 1) |
| 23 | |
| 24 | void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) |
| 25 | { |
| 26 | printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n"); |
| 27 | |
| 28 | RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20); |
| 29 | if (vcp & VC_ACTIVE) |
| 30 | RCBA32_OR(CIR0050, 1 << 19 | 1 << 17); |
| 31 | |
| 32 | RCBA32(CIR0050); /* Ensure posted write hits */ |
| 33 | |
| 34 | /* Use the same virtual channel mapping on both ends of the DMI link */ |
| 35 | RCBA32(V0CTL) = vc0; |
| 36 | RCBA32(V1CTL) = vc1; |
| 37 | RCBA32(V1CTL); /* Ensure posted write hits */ |
| 38 | RCBA32(VPCTL) = vcp; |
| 39 | RCBA32(VPCTL); /* Ensure posted write hits */ |
| 40 | RCBA32(VMCTL) = vcm; |
| 41 | |
| 42 | /* Lock the registers */ |
| 43 | RCBA32_OR(CIR0050, 1U << 31); |
| 44 | RCBA32(CIR0050); /* Ensure posted write hits */ |
| 45 | |
| 46 | printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... "); |
| 47 | do {} while (RCBA16(V0STS) & VCNEGPND); |
| 48 | do {} while (RCBA16(V1STS) & VCNEGPND); |
| 49 | do {} while (RCBA16(VPSTS) & VCNEGPND); |
| 50 | do {} while (RCBA16(VMSTS) & VCNEGPND); |
| 51 | printk(BIOS_DEBUG, "done!\n"); |
| 52 | } |