blob: 96b4c5d9a92700f18cae5d1b2b953da6fd4338da [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20extern struct chip_operations cpu_intel_model_206ax_ops;
21
22/* Magic value used to locate this chip in the device tree */
23#define SPEEDSTEP_APIC_MAGIC 0xACAC
24
25struct cpu_intel_model_206ax_config {
26 u8 disable_acpi; /* Do not generate CPU ACPI tables */
27
28 u8 pstate_coord_type; /* Processor Coordination Type */
29
30 int c1_battery; /* ACPI C1 on Battery Power */
31 int c2_battery; /* ACPI C2 on Battery Power */
32 int c3_battery; /* ACPI C3 on Battery Power */
33
34 int c1_acpower; /* ACPI C1 on AC Power */
35 int c2_acpower; /* ACPI C2 on AC Power */
36 int c3_acpower; /* ACPI C3 on AC Power */
Duncan Laurie55632112012-07-16 12:19:00 -070037
38 int tcc_offset; /* TCC Activation Offset */
Stefan Reinauer5c554632012-04-04 00:09:50 +020039};