blob: 532680b0ef72aff2cef06003f25af26ded3ba4c0 [file] [log] [blame]
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06001chip soc/intel/baytrail
2
Matt DeVillier667d8af2017-01-07 23:46:41 -06003 # IGD Displays
4 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
5
Elyes HAOUAS808fc8e2018-05-28 13:30:59 +02006 # SATA port enable mask (2 ports)
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06007 register "sata_port_map" = "0x1"
8 register "sata_ahci" = "0x1"
9 register "ide_legacy_combined" = "0x0"
10
11 # Route USB ports to XHCI
12 register "usb_route_to_xhci" = "1"
13
14 # USB Port Disable Mask
15 register "usb2_port_disable_mask" = "0x0"
16 register "usb3_port_disable_mask" = "0x0"
17
18 # USB PHY settings
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060019 register "usb2_per_port_lane0" = "0x00049a09"
20 register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
21 register "usb2_per_port_lane1" = "0x00049a09"
22 register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
23 register "usb2_per_port_lane2" = "0x00049209"
24 register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
25 register "usb2_per_port_lane3" = "0x00049a09"
26 register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
27
28 # LPE audio codec settings
29 register "lpe_codec_clk_freq" = "25" # 25MHz clock
30 register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
31
32 # SD Card controller
33 register "sdcard_cap_low" = "0x036864b2"
34 register "sdcard_cap_high" = "0x0"
35
36 # Enable devices in ACPI mode
37 register "lpe_acpi_mode" = "1"
38 register "lpss_acpi_mode" = "1"
39 register "scc_acpi_mode" = "1"
40
41 # Enable PIPEA as DP_C
42 register "gpu_pipea_port_select" = "2" # DP_C
43 register "gpu_pipea_power_cycle_delay" = "6" # 600ms
44 register "gpu_pipea_power_on_delay" = "5000" # 500ms
45 register "gpu_pipea_light_on_delay" = "70" # 7ms
46 register "gpu_pipea_power_off_delay" = "500" # 50ms
47 register "gpu_pipea_light_off_delay" = "2000" # 200ms
48
49 # VR PS2 control
50 register "vnn_ps2_enable" = "1"
51 register "vcc_ps2_enable" = "1"
52
53 # Disable SLP_X stretching after SUS power well fail.
54 register "disable_slp_x_stretch_sus_fail" = "1"
55
Arthur Heymans69cd7292022-11-07 13:52:11 +010056 device cpu_cluster 0 on end
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060057 device domain 0 on
58 device pci 00.0 on end # SoC router
59 device pci 02.0 on end # GFX
Mate Kukri45b51e02020-07-03 14:44:49 +020060 device pci 10.0 off end # MMC
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060061 device pci 11.0 off end # SDIO
62 device pci 12.0 on end # SD
63 device pci 13.0 on end # SATA
64 device pci 14.0 on end # XHCI
65 device pci 15.0 on end # LPE
Mate Kukri45b51e02020-07-03 14:44:49 +020066 device pci 17.0 on end # MMC45
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060067 device pci 18.0 on end # SIO_DMA1
68 device pci 18.1 on end # I2C1
69 device pci 18.2 on end # I2C2
70 device pci 18.3 off end # I2C3
71 device pci 18.4 off end # I2C4
Matt DeVillierf848ed02017-04-07 17:39:40 -050072 device pci 18.5 off end # I2C5
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060073 device pci 18.6 off end # I2C6
74 device pci 18.7 off end # I2C7
Matt DeVillier5ff460f2018-08-01 21:32:36 -050075 device pci 1a.0 off end # TXE
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060076 device pci 1b.0 on end # HDA
77 device pci 1c.0 on end # PCIE_PORT1
Matt DeVillier1d6e0732020-03-31 17:37:12 -050078 device pci 1c.1 off end # PCIE_PORT2
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060079 device pci 1c.2 off end # PCIE_PORT3
80 device pci 1c.3 off end # PCIE_PORT4
81 device pci 1d.0 on end # EHCI
82 device pci 1e.0 on end # SIO_DMA2
83 device pci 1e.1 off end # PWM1
84 device pci 1e.2 off end # PWM2
85 device pci 1e.3 off end # HSUART1
86 device pci 1e.4 off end # HSUART2
87 device pci 1e.5 off end # SPI
88 device pci 1f.0 on
Matt DeVillier3044af72018-08-01 13:05:14 -050089 chip drivers/pc80/tpm
90 device pnp 0c31.0 on end
91 end
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060092 chip ec/google/chromeec
93 # We only have one init function that
94 # we need to call to initialize the
95 # keyboard part of the EC.
96 device pnp ff.1 on # dummy address
97 end
98 end
99 end # LPC Bridge
100 device pci 1f.3 off end # SMBus
101 end
102end