Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * The sole purpose of this driver is to avoid BAR to be changed during |
| 19 | * resource allocation. Since configuration space is just 32 bytes it |
| 20 | * shouldn't cause any fragmentation. |
| 21 | */ |
| 22 | |
| 23 | #include <console/uart.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <soc/pci_devs.h> |
| 28 | #include <console/console.h> |
Julien Viard de Galbert | 546923f | 2018-03-05 11:10:16 +0100 | [diff] [blame^] | 29 | #include <soc/uart.h> |
| 30 | #include <fsp/api.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 31 | |
| 32 | static void dnv_ns_uart_read_resources(struct device *dev) |
| 33 | { |
| 34 | /* read resources to be visible in the log*/ |
| 35 | pci_dev_read_resources(dev); |
Julien Viard de Galbert | 546923f | 2018-03-05 11:10:16 +0100 | [diff] [blame^] | 36 | if (!IS_ENABLED(CONFIG_LEGACY_UART_MODE)) |
| 37 | return; |
| 38 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 39 | if (res == NULL) |
| 40 | return; |
| 41 | res->size = 0x8; |
| 42 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 43 | /* Do not configure membar */ |
| 44 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 45 | if (res != NULL) |
| 46 | res->flags = 0; |
| 47 | compact_resources(dev); |
| 48 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | static struct device_operations uart_ops = { |
| 52 | .read_resources = dnv_ns_uart_read_resources, |
| 53 | .set_resources = pci_dev_set_resources, |
| 54 | .enable_resources = pci_dev_enable_resources, |
| 55 | .init = pci_dev_init, |
| 56 | .enable = DEVICE_NOOP |
| 57 | }; |
| 58 | |
| 59 | static const unsigned short uart_ids[] = { |
| 60 | HSUART_DEVID, /* HSUART 0/1/2 */ |
| 61 | 0 |
| 62 | }; |
| 63 | |
| 64 | static const struct pci_driver uart_driver __pci_driver = { |
| 65 | .ops = &uart_ops, |
| 66 | .vendor = PCI_VENDOR_ID_INTEL, |
| 67 | .devices = uart_ids |
| 68 | }; |
Julien Viard de Galbert | 546923f | 2018-03-05 11:10:16 +0100 | [diff] [blame^] | 69 | |
| 70 | static void hide_hsuarts(void) |
| 71 | { |
| 72 | int i; |
| 73 | printk(BIOS_DEBUG, "HIDING HSUARTs.\n"); |
| 74 | /* There is a hardware requirement to hide functions starting from the |
| 75 | last one. */ |
| 76 | for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) { |
| 77 | struct device *uart_dev; |
| 78 | uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i)); |
| 79 | if (uart_dev == NULL) |
| 80 | continue; |
| 81 | pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1); |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | /* Hide HSUART PCI device very last when FSP no longer needs it */ |
| 86 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
| 87 | { |
| 88 | if (phase != END_OF_FIRMWARE) |
| 89 | return; |
| 90 | if (IS_ENABLED(CONFIG_LEGACY_UART_MODE)) |
| 91 | hide_hsuarts(); |
| 92 | } |