Zheng Bao | 1ad9f29 | 2010-04-23 17:37:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <boot/tables.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/amd/mtrr.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <southbridge/amd/sb700/sb700.h> |
| 29 | #include "chip.h" |
| 30 | |
| 31 | #define ADT7461_ADDRESS 0x4C |
| 32 | #define ARA_ADDRESS 0x0C /* Alert Response Address */ |
| 33 | |
| 34 | extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); |
| 35 | extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, |
| 36 | u8 val); |
| 37 | |
| 38 | #define ADT7461_read_byte(address) \ |
| 39 | do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) |
| 40 | #define ARA_read_byte(address) \ |
| 41 | do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) |
| 42 | #define ADT7461_write_byte(address, val) \ |
| 43 | do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) |
| 44 | |
| 45 | #define SMBUS_IO_BASE 0x6000 |
| 46 | |
| 47 | uint64_t uma_memory_base, uma_memory_size; |
| 48 | |
| 49 | void set_pcie_dereset(void); |
| 50 | void set_pcie_reset(void); |
Wang Qing Pei | 543f767 | 2010-08-17 11:11:09 +0000 | [diff] [blame^] | 51 | u8 is_dev3_present(void); |
Zheng Bao | 1ad9f29 | 2010-04-23 17:37:41 +0000 | [diff] [blame] | 52 | |
| 53 | void set_pcie_dereset() |
| 54 | { |
| 55 | u8 byte; |
| 56 | u16 word; |
| 57 | device_t sm_dev; |
| 58 | /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ |
| 59 | /* set 0 to bit2 :disable GPM8 as AZ_RST output */ |
| 60 | byte = pm_ioread(0x8d); |
| 61 | byte &= ~((1 << 1) | (1 << 2)); |
| 62 | pm_iowrite(0x8d, byte); |
| 63 | |
| 64 | /* set the GPM8 and GPM9 output enable and the value to 1 */ |
| 65 | byte = pm_ioread(0x94); |
| 66 | byte &= ~((1 << 2) | (1 << 3)); |
| 67 | byte |= ((1 << 0) | (1 << 1)); |
| 68 | pm_iowrite(0x94, byte); |
| 69 | |
| 70 | /* set the GPIO65 output enable and the value is 1 */ |
| 71 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 72 | word = pci_read_config16(sm_dev, 0x7e); |
| 73 | word |= (1 << 0); |
| 74 | word &= ~(1 << 4); |
| 75 | pci_write_config16(sm_dev, 0x7e, word); |
| 76 | } |
| 77 | |
| 78 | void set_pcie_reset() |
| 79 | { |
| 80 | u8 byte; |
| 81 | u16 word; |
| 82 | device_t sm_dev; |
| 83 | |
| 84 | /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ |
| 85 | /* set 0 to bit2 :disable GPM8 as AZ_RST output */ |
| 86 | byte = pm_ioread(0x8d); |
| 87 | byte &= ~((1 << 1) | (1 << 2)); |
| 88 | pm_iowrite(0x8d, byte); |
| 89 | |
| 90 | /* set the GPM8 and GPM9 output enable and the value to 0 */ |
| 91 | byte = pm_ioread(0x94); |
| 92 | byte &= ~((1 << 2) | (1 << 3)); |
| 93 | byte &= ~((1 << 0) | (1 << 1)); |
| 94 | pm_iowrite(0x94, byte); |
| 95 | |
| 96 | /* set the GPIO65 output enable and the value is 0 */ |
| 97 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 98 | word = pci_read_config16(sm_dev, 0x7e); |
| 99 | word &= ~(1 << 0); |
| 100 | word &= ~(1 << 4); |
| 101 | pci_write_config16(sm_dev, 0x7e, word); |
| 102 | } |
| 103 | |
| 104 | #if 0 /* TODO: */ |
| 105 | /******************************************************** |
| 106 | * tilapia uses SB700 GPIO8 to detect IDE_DMA66. |
| 107 | * IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to |
| 108 | * get the cable type, 40 pin or 80 pin? |
| 109 | ********************************************************/ |
| 110 | static void get_ide_dma66(void) |
| 111 | { |
| 112 | u8 byte; |
| 113 | /*u32 sm_dev, ide_dev; */ |
| 114 | device_t sm_dev, ide_dev; |
| 115 | |
| 116 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 117 | |
| 118 | byte = pci_read_config8(sm_dev, 0xA9); |
| 119 | byte |= (1 << 4); /* Set Gpio8 as input */ |
| 120 | pci_write_config8(sm_dev, 0xA9, byte); |
| 121 | |
| 122 | ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); |
| 123 | byte = pci_read_config8(ide_dev, 0x56); |
| 124 | byte &= ~(7 << 0); |
| 125 | if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) |
| 126 | byte |= 2 << 0; /* mode 2 */ |
| 127 | else |
| 128 | byte |= 5 << 0; /* mode 5 */ |
| 129 | pci_write_config8(ide_dev, 0x56, byte); |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | /* |
Wang Qing Pei | 543f767 | 2010-08-17 11:11:09 +0000 | [diff] [blame^] | 134 | * justify the dev3 is exist or not |
| 135 | */ |
| 136 | u8 is_dev3_present(void) |
| 137 | { |
| 138 | u16 word; |
| 139 | device_t sm_dev; |
| 140 | |
| 141 | /* access the smbus extended register */ |
| 142 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 143 | |
| 144 | /* put the GPIO68 output to tristate */ |
| 145 | word = pci_read_config16(sm_dev, 0x7e); |
| 146 | word |= 1 << 6; |
| 147 | pci_write_config16(sm_dev, 0x7e,word); |
| 148 | |
| 149 | /* read the GPIO68 input status */ |
| 150 | word = pci_read_config16(sm_dev, 0x7e); |
| 151 | |
| 152 | if(word & (1 << 10)){ |
| 153 | /*not exist*/ |
| 154 | return 0; |
| 155 | }else{ |
| 156 | /*exist*/ |
| 157 | return 1; |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | |
| 162 | /* |
| 163 | * set gpio40 gfx |
| 164 | */ |
| 165 | static void set_gpio40_gfx(void) |
| 166 | { |
| 167 | u8 byte; |
| 168 | u32 dword; |
| 169 | device_t sm_dev; |
| 170 | /* disable the GPIO40 as CLKREQ2# function */ |
| 171 | byte = pm_ioread(0xd3); |
| 172 | byte &= ~(1 << 7); |
| 173 | pm_iowrite(0xd3, byte); |
| 174 | |
| 175 | /* disable the GPIO40 as CLKREQ3# function */ |
| 176 | byte = pm_ioread(0xd4); |
| 177 | byte &= ~(1 << 0); |
| 178 | pm_iowrite(0xd4, byte); |
| 179 | |
| 180 | /* enable pull up for GPIO68 */ |
| 181 | byte = pm2_ioread(0xf1); |
| 182 | byte &= ~(1 << 4); |
| 183 | pm2_iowrite(0xf1, byte); |
| 184 | |
| 185 | /* access the smbus extended register */ |
| 186 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 187 | |
| 188 | /*if the dev3 is present, set the gfx to 2x8 lanes*/ |
| 189 | /*otherwise set the gfx to 1x16 lanes*/ |
| 190 | if(is_dev3_present()){ |
| 191 | |
| 192 | printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); |
| 193 | /* when the gpio40 is configured as GPIO, this will enable the output */ |
| 194 | pci_write_config32(sm_dev, 0xf8, 0x4); |
| 195 | dword = pci_read_config32(sm_dev, 0xfc); |
| 196 | dword &= ~(1 << 10); |
| 197 | |
| 198 | /* When the gpio40 is configured as GPIO, this will represent the output value*/ |
| 199 | /* 1 :enable two x8 , 0 : master slot enable only */ |
| 200 | dword |= (1 << 26); |
| 201 | pci_write_config32(sm_dev, 0xfc, dword); |
| 202 | |
| 203 | }else{ |
| 204 | printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); |
| 205 | /* when the gpio40 is configured as GPIO, this will enable the output */ |
| 206 | pci_write_config32(sm_dev, 0xf8, 0x4); |
| 207 | dword = pci_read_config32(sm_dev, 0xfc); |
| 208 | dword &= ~(1 << 10); |
| 209 | |
| 210 | /* When the gpio40 is configured as GPIO, this will represent the output value*/ |
| 211 | /* 1 :enable two x8 , 0 : master slot enable only */ |
| 212 | dword &= ~(1 << 26); |
| 213 | pci_write_config32(sm_dev, 0xfc, dword); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | /* |
Zheng Bao | 1ad9f29 | 2010-04-23 17:37:41 +0000 | [diff] [blame] | 218 | * set thermal config |
| 219 | */ |
| 220 | static void set_thermal_config(void) |
| 221 | { |
| 222 | u8 byte; |
| 223 | u16 word; |
| 224 | device_t sm_dev; |
| 225 | |
| 226 | /* set ADT 7461 */ |
| 227 | ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ |
| 228 | ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ |
| 229 | ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ |
| 230 | ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ |
| 231 | |
| 232 | ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ |
| 233 | ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ |
| 234 | |
| 235 | byte = ADT7461_read_byte(0x02); /* read status register to clear it */ |
| 236 | ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ |
| 237 | printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); |
| 238 | |
| 239 | /* sb700 settings for thermal config */ |
| 240 | /* set SB700 GPIO 64 to GPIO with pull-up */ |
| 241 | byte = pm2_ioread(0x42); |
| 242 | byte &= 0x3f; |
| 243 | pm2_iowrite(0x42, byte); |
| 244 | |
| 245 | /* set GPIO 64 to input */ |
| 246 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 247 | word = pci_read_config16(sm_dev, 0x56); |
| 248 | word |= 1 << 7; |
| 249 | pci_write_config16(sm_dev, 0x56, word); |
| 250 | |
| 251 | /* set GPIO 64 internal pull-up */ |
| 252 | byte = pm2_ioread(0xf0); |
| 253 | byte &= 0xee; |
| 254 | pm2_iowrite(0xf0, byte); |
| 255 | |
| 256 | /* set Talert to be active low */ |
| 257 | byte = pm_ioread(0x67); |
| 258 | byte &= ~(1 << 5); |
| 259 | pm_iowrite(0x67, byte); |
| 260 | |
| 261 | /* set Talert to generate ACPI event */ |
| 262 | byte = pm_ioread(0x3c); |
| 263 | byte &= 0xf3; |
| 264 | pm_iowrite(0x3c, byte); |
| 265 | |
| 266 | /* THERMTRIP pin */ |
| 267 | /* byte = pm_ioread(0x68); |
| 268 | * byte |= 1 << 3; |
| 269 | * pm_iowrite(0x68, byte); |
| 270 | * |
| 271 | * byte = pm_ioread(0x55); |
| 272 | * byte |= 1 << 0; |
| 273 | * pm_iowrite(0x55, byte); |
| 274 | * |
| 275 | * byte = pm_ioread(0x67); |
| 276 | * byte &= ~( 1 << 6); |
| 277 | * pm_iowrite(0x67, byte); |
| 278 | */ |
| 279 | } |
| 280 | |
| 281 | /************************************************* |
| 282 | * enable the dedicated function in tilapia board. |
| 283 | * This function called early than rs780_enable. |
| 284 | *************************************************/ |
| 285 | static void tilapia_enable(device_t dev) |
| 286 | { |
| 287 | /* Leave it for furture use. */ |
| 288 | /* struct mainboard_config *mainboard = |
| 289 | (struct mainboard_config *)dev->chip_info; */ |
| 290 | |
| 291 | printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); |
| 292 | |
| 293 | #if (CONFIG_GFXUMA == 1) |
| 294 | msr_t msr, msr2; |
| 295 | |
| 296 | /* TOP_MEM: the top of DRAM below 4G */ |
| 297 | msr = rdmsr(TOP_MEM); |
| 298 | printk(BIOS_INFO, |
| 299 | "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 300 | __func__, msr.lo, msr.hi); |
| 301 | |
| 302 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 303 | msr2 = rdmsr(TOP_MEM2); |
| 304 | printk(BIOS_INFO, |
| 305 | "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", |
| 306 | __func__, msr2.lo, msr2.hi); |
| 307 | |
| 308 | switch (msr.lo) { |
| 309 | case 0x10000000: /* 256M system memory */ |
| 310 | uma_memory_size = 0x4000000; /* 64M recommended UMA */ |
| 311 | break; |
| 312 | |
| 313 | case 0x20000000: /* 512M system memory */ |
| 314 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 315 | break; |
| 316 | |
| 317 | default: /* 1GB and above system memory */ |
| 318 | uma_memory_size = 0x10000000; /* 256M recommended UMA */ |
| 319 | break; |
| 320 | } |
| 321 | |
| 322 | uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ |
| 323 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 324 | __func__, uma_memory_size, uma_memory_base); |
| 325 | |
| 326 | /* TODO: TOP_MEM2 */ |
| 327 | #else |
| 328 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 329 | uma_memory_base = 0x38000000; /* 1GB system memory supposed */ |
| 330 | #endif |
| 331 | |
| 332 | set_pcie_dereset(); |
| 333 | /* get_ide_dma66(); */ |
| 334 | set_thermal_config(); |
Wang Qing Pei | 543f767 | 2010-08-17 11:11:09 +0000 | [diff] [blame^] | 335 | set_gpio40_gfx(); |
Zheng Bao | 1ad9f29 | 2010-04-23 17:37:41 +0000 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | int add_mainboard_resources(struct lb_memory *mem) |
| 339 | { |
| 340 | /* UMA is removed from system memory in the northbridge code, but |
| 341 | * in some circumstances we want the memory mentioned as reserved. |
| 342 | */ |
| 343 | #if (CONFIG_GFXUMA == 1) |
| 344 | printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", |
| 345 | uma_memory_base, uma_memory_size); |
| 346 | lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, |
| 347 | uma_memory_size); |
| 348 | #endif |
| 349 | return 0; |
| 350 | } |
| 351 | |
| 352 | struct chip_operations mainboard_ops = { |
| 353 | CHIP_NAME("AMD TILAPIA Mainboard") |
| 354 | .enable_dev = tilapia_enable, |
| 355 | }; |