Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2, or (at your option) |
| 9 | * any later verion of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 17 | #include <arch/acpi.h> |
| 18 | #include <types.h> |
| 19 | #include <string.h> |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
Patrick Rudolph | bac2303 | 2017-06-30 15:18:23 +0200 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <cbmem.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 26 | #include "intel_bios.h" |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 27 | #include "opregion.h" |
| 28 | |
| 29 | /* Write ASLS PCI register and prepare SWSCI register. */ |
| 30 | void intel_gma_opregion_register(uintptr_t opregion) |
| 31 | { |
| 32 | device_t igd; |
| 33 | u16 reg16; |
| 34 | |
| 35 | igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); |
| 36 | if (!igd || !igd->enabled) |
| 37 | return; |
| 38 | |
| 39 | /* |
| 40 | * Intel BIOS Specification |
| 41 | * Chapter 5.3.7 "Initialize Hardware State" |
| 42 | */ |
| 43 | pci_write_config32(igd, ASLS, opregion); |
| 44 | |
| 45 | /* |
| 46 | * Intel's Windows driver relies on this: |
| 47 | * Intel BIOS Specification |
| 48 | * Chapter 5.4 "ASL Software SCI Handler" |
| 49 | */ |
| 50 | reg16 = pci_read_config16(igd, SWSCI); |
| 51 | reg16 &= ~GSSCIE; |
| 52 | reg16 |= SMISCISEL; |
| 53 | pci_write_config16(igd, SWSCI, reg16); |
| 54 | } |
Patrick Rudolph | bac2303 | 2017-06-30 15:18:23 +0200 | [diff] [blame] | 55 | |
| 56 | /* Restore ASLS register on S3 resume and prepare SWSCI. */ |
| 57 | void intel_gma_restore_opregion(void) |
| 58 | { |
| 59 | if (acpi_is_wakeup_s3()) { |
| 60 | const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 61 | uintptr_t aslb; |
| 62 | |
| 63 | if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs))) |
| 64 | intel_gma_opregion_register(aslb); |
| 65 | else |
| 66 | printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n"); |
| 67 | } |
| 68 | } |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 69 | |
| 70 | static void *get_intel_vbios(void) |
| 71 | { |
| 72 | /* This should probably be looking at CBFS or we should always |
| 73 | * deploy the VBIOS on Intel systems, even if we don't run it |
| 74 | * in coreboot (e.g. SeaBIOS only scenarios). |
| 75 | */ |
| 76 | u8 *vbios = (u8 *)0xc0000; |
| 77 | |
| 78 | optionrom_header_t *oprom = (optionrom_header_t *)vbios; |
| 79 | optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios + |
| 80 | oprom->pcir_offset); |
| 81 | |
| 82 | printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n", |
| 83 | oprom->signature, pcir->vendor, pcir->classcode[0], |
| 84 | pcir->classcode[1], pcir->classcode[2]); |
| 85 | |
| 86 | |
| 87 | if ((oprom->signature == OPROM_SIGNATURE) && |
| 88 | (pcir->vendor == PCI_VENDOR_ID_INTEL) && |
| 89 | (pcir->classcode[0] == 0x00) && |
| 90 | (pcir->classcode[1] == 0x00) && |
| 91 | (pcir->classcode[2] == 0x03)) |
| 92 | return (void *)vbios; |
| 93 | |
| 94 | return NULL; |
| 95 | } |
| 96 | |
| 97 | static enum cb_err init_opregion_vbt(igd_opregion_t *opregion) |
| 98 | { |
| 99 | void *vbios; |
| 100 | vbios = get_intel_vbios(); |
| 101 | if (!vbios) { |
| 102 | printk(BIOS_DEBUG, "VBIOS not found.\n"); |
| 103 | return CB_ERR; |
| 104 | } |
| 105 | |
| 106 | printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios); |
| 107 | optionrom_header_t *oprom = (optionrom_header_t *)vbios; |
| 108 | optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios + |
| 109 | oprom->vbt_offset); |
| 110 | |
| 111 | if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { |
| 112 | printk(BIOS_DEBUG, "VBT not found!\n"); |
| 113 | return CB_ERR; |
| 114 | } |
| 115 | |
| 116 | memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); |
| 117 | memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ? |
| 118 | vbt->hdr_vbt_size : 7168); |
| 119 | |
| 120 | return CB_SUCCESS; |
| 121 | } |
| 122 | |
| 123 | /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ |
| 124 | enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion) |
| 125 | { |
| 126 | enum cb_err ret; |
| 127 | |
| 128 | memset((void *)opregion, 0, sizeof(igd_opregion_t)); |
| 129 | |
| 130 | // FIXME if IGD is disabled, we should exit here. |
| 131 | |
| 132 | memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, |
| 133 | sizeof(opregion->header.signature)); |
| 134 | |
| 135 | /* 8kb */ |
| 136 | opregion->header.size = sizeof(igd_opregion_t) / 1024; |
| 137 | opregion->header.version = IGD_OPREGION_VERSION; |
| 138 | |
| 139 | // FIXME We just assume we're mobile for now |
| 140 | opregion->header.mailboxes = MAILBOXES_MOBILE; |
| 141 | |
| 142 | // TODO Initialize Mailbox 1 |
| 143 | |
| 144 | // TODO Initialize Mailbox 3 |
| 145 | opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; |
| 146 | opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; |
| 147 | opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e |
| 148 | opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; |
| 149 | opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; |
| 150 | opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; |
| 151 | opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; |
| 152 | opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; |
| 153 | opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; |
| 154 | opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; |
| 155 | opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; |
| 156 | opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; |
| 157 | opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; |
| 158 | opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; |
| 159 | opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; |
| 160 | |
| 161 | ret = init_opregion_vbt(opregion); |
| 162 | if (ret != CB_SUCCESS) |
| 163 | return ret; |
| 164 | |
| 165 | /* Write ASLS PCI register and prepare SWSCI register. */ |
| 166 | intel_gma_opregion_register((uintptr_t)opregion); |
| 167 | |
| 168 | return CB_SUCCESS; |
| 169 | } |