Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * Copyright (C) 2017 Alexander Couzens <lynxis@fe80.eu> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <string.h> |
| 21 | #include <lib.h> |
| 22 | #include <timestamp.h> |
| 23 | #include <arch/byteorder.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pnp_def.h> |
| 27 | #include <cpu/x86/lapic.h> |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 29 | #include <console/console.h> |
| 30 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 31 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 32 | #include <southbridge/intel/bd82x6x/pch.h> |
| 33 | #include <southbridge/intel/common/gpio.h> |
| 34 | #include <arch/cpu.h> |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 35 | #include <cbfs.h> |
| 36 | |
| 37 | void pch_enable_lpc(void) |
| 38 | { |
| 39 | /* X230 EC Decode Range Port60/64, Port62/66 */ |
| 40 | /* Enable EC, PS/2 Keyboard/Mouse */ |
| 41 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
Patrick Rudolph | 93eac6a | 2017-05-04 19:10:50 +0200 | [diff] [blame] | 42 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 43 | |
| 44 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); |
| 45 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); |
| 46 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); |
| 47 | |
Patrick Rudolph | ac27d36 | 2017-05-04 19:00:33 +0200 | [diff] [blame] | 48 | pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 52 | /* enabled, current, OC pin */ |
| 53 | { 0, 3, 0 }, /* P00 disconnected */ |
| 54 | { 1, 1, 1 }, /* P01 left or right */ |
| 55 | { 0, 1, 3 }, /* P02 disconnected */ |
| 56 | { 1, 3, -1 },/* P03 WWAN */ |
| 57 | { 0, 1, 2 }, /* P04 disconnected */ |
| 58 | { 0, 1, -1 },/* P05 disconnected */ |
| 59 | { 0, 1, -1 },/* P06 disconnected */ |
| 60 | { 0, 2, -1 },/* P07 disconnected */ |
| 61 | { 0, 1, -1 },/* P08 disconnected */ |
| 62 | { 1, 2, 5 }, /* P09 left or right */ |
| 63 | { 1, 3, -1 },/* P10 FPR */ |
| 64 | { 1, 3, -1 },/* P11 Bluetooth */ |
| 65 | { 1, 1, -1 },/* P12 WLAN */ |
| 66 | { 1, 1, -1 },/* P13 Camera */ |
| 67 | }; |
| 68 | |
| 69 | static uint8_t *get_spd_data(int spd_index) |
| 70 | { |
| 71 | uint8_t *spd_file; |
| 72 | size_t spd_file_len; |
| 73 | |
| 74 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
| 75 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 76 | &spd_file_len); |
| 77 | if (!spd_file) |
| 78 | die("SPD data not found."); |
| 79 | |
| 80 | if (spd_file_len < spd_index * 256) |
| 81 | die("Missing SPD data."); |
| 82 | |
| 83 | return spd_file + spd_index * 256; |
| 84 | } |
| 85 | |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 86 | void mainboard_rcba_config(void) |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 87 | { |
| 88 | } |
| 89 | |
| 90 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 91 | { |
| 92 | uint8_t *memory; |
| 93 | const int spd_gpio_vector[] = {25, 45, -1}; |
| 94 | int spd_index = get_gpios(spd_gpio_vector); |
| 95 | |
| 96 | /* 4gb model = 0, 8gb model = 1 */ |
| 97 | /* int extended_memory_version = get_gpio(44); */ |
| 98 | /* TODO: how do they differ? Guess only one slot is connected */ |
| 99 | |
| 100 | /* |
| 101 | * GPIO45 GPIO25 |
| 102 | * 0 0 elpida |
| 103 | * 0 1 hynix |
| 104 | * 1 0 samsung |
| 105 | * 1 1 reserved |
| 106 | */ |
| 107 | |
Nico Huber | e9787ff | 2017-08-05 19:26:29 +0200 | [diff] [blame] | 108 | /* We only support elpida and samsung. |
| 109 | Because the spd data is missing. */ |
| 110 | if (spd_index != 0 && spd_index != 2) |
Alexander Couzens | db50856 | 2016-10-12 04:44:19 +0200 | [diff] [blame] | 111 | die("Unsupported Memory. Please add your SPD dump to coreboot."); |
| 112 | |
| 113 | memory = get_spd_data(spd_index); |
| 114 | memcpy(&spd[0], memory, 256); |
| 115 | memcpy(&spd[2], memory, 256); |
| 116 | } |
| 117 | |
| 118 | void mainboard_early_init(int s3resume) |
| 119 | { |
| 120 | } |
| 121 | |
| 122 | void mainboard_config_superio(void) |
| 123 | { |
| 124 | } |