Michał Żygowski | c25f00a | 2023-06-16 11:22:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
| 4 | #include <device/device.h> |
| 5 | #include <identity.h> |
| 6 | #include <soc/pci_devs.h> |
| 7 | #include <soc/ramstage.h> |
| 8 | #include <smbios.h> |
| 9 | #include <string.h> |
| 10 | |
| 11 | |
| 12 | void mainboard_fill_fadt(acpi_fadt_t *fadt) |
| 13 | { |
| 14 | fadt->preferred_pm_profile = PM_DESKTOP; |
| 15 | fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 16 | } |
| 17 | |
| 18 | static void mainboard_init(void *chip_info) |
| 19 | { |
Michał Żygowski | c25f00a | 2023-06-16 11:22:04 +0200 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | u8 smbios_mainboard_feature_flags(void) |
| 23 | { |
| 24 | return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; |
| 25 | } |
| 26 | |
| 27 | smbios_wakeup_type smbios_system_wakeup_type(void) |
| 28 | { |
| 29 | return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; |
| 30 | } |
| 31 | |
| 32 | const char *smbios_system_product_name(void) |
| 33 | { |
| 34 | return "MS-7E06"; |
| 35 | } |
| 36 | |
| 37 | const char *smbios_mainboard_product_name(void) |
| 38 | { |
| 39 | if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) { |
| 40 | if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) |
| 41 | return "PRO Z790-P WIFI DDR4(MS-7E06)"; |
| 42 | else |
| 43 | return "PRO Z790-P DDR4(MS-7E06)"; |
| 44 | } |
| 45 | |
| 46 | if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) { |
| 47 | if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) |
| 48 | return "PRO Z790-P WIFI (MS-7E06)"; |
| 49 | else |
| 50 | return "PRO Z790-P (MS-7E06)"; |
| 51 | } |
| 52 | |
| 53 | return CONFIG_MAINBOARD_PART_NUMBER; |
| 54 | } |
| 55 | |
| 56 | /* Only baseboard serial number is populated */ |
| 57 | const char *smbios_system_serial_number(void) |
| 58 | { |
| 59 | return "Default string"; |
| 60 | } |
| 61 | |
| 62 | const char *smbios_system_sku(void) |
| 63 | { |
| 64 | return "Default string"; |
| 65 | } |
| 66 | |
| 67 | void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 68 | { |
| 69 | uint8_t aspm, aspm_l1; |
| 70 | |
| 71 | if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM)) |
| 72 | aspm_l1 = 2; // 2 - L1.1 and L1.2 |
| 73 | else |
| 74 | aspm_l1 = 0; |
| 75 | |
| 76 | if (CONFIG(PCIEXP_ASPM)) { |
| 77 | aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s |
| 78 | } else { |
| 79 | aspm = 0; |
| 80 | aspm_l1 = 0; |
| 81 | } |
| 82 | |
| 83 | memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); |
| 84 | memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm)); |
| 85 | memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating)); |
| 86 | memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating)); |
| 87 | |
| 88 | params->UsbPdoProgramming = 1; |
| 89 | params->CpuPcieFiaProgramming = 1; |
| 90 | params->PcieRpFunctionSwap = 0; |
| 91 | params->CpuPcieRpFunctionSwap = 0; |
| 92 | params->PchLegacyIoLowLatency = 1; |
| 93 | params->PchDmiAspmCtrl = 0; |
| 94 | |
| 95 | params->CpuPcieRpPmSci[0] = 0; // M2_1 |
| 96 | params->CpuPcieRpPmSci[1] = 0; // PCI_E1 |
| 97 | params->PcieRpPmSci[0] = 0; // PCI_E2 |
| 98 | params->PcieRpPmSci[1] = 0; // PCI_E4 |
| 99 | params->PcieRpPmSci[2] = 0; // Ethernet |
| 100 | params->PcieRpPmSci[4] = 0; // PCI_E3 |
| 101 | params->PcieRpPmSci[8] = 0; // M2_3 |
| 102 | params->PcieRpPmSci[20] = 0; // M2_4 |
| 103 | params->PcieRpPmSci[24] = 0; // M2_2 |
| 104 | |
| 105 | params->PcieRpMaxPayload[0] = 1; // PCI_E2 |
| 106 | params->PcieRpMaxPayload[1] = 1; // PCI_E4 |
| 107 | params->PcieRpMaxPayload[2] = 1; // Ethernet |
| 108 | params->PcieRpMaxPayload[4] = 1; // PCI_E3 |
| 109 | params->PcieRpMaxPayload[8] = 1; // M2_3 |
| 110 | params->PcieRpMaxPayload[20] = 1; // M2_4 |
| 111 | params->PcieRpMaxPayload[24] = 1; // M2_2 |
| 112 | |
| 113 | params->CpuPcieRpTransmitterHalfSwing[0] = 1; // M2_1 |
| 114 | params->CpuPcieRpTransmitterHalfSwing[1] = 1; // PCI_E1 |
| 115 | params->PcieRpTransmitterHalfSwing[0] = 1; // PCI_E2 |
| 116 | params->PcieRpTransmitterHalfSwing[1] = 1; // PCI_E4 |
| 117 | params->PcieRpTransmitterHalfSwing[2] = 1; // Ethernet |
| 118 | params->PcieRpTransmitterHalfSwing[4] = 1; // PCI_E3 |
| 119 | params->PcieRpTransmitterHalfSwing[8] = 1; // M2_3 |
| 120 | params->PcieRpTransmitterHalfSwing[20] = 1; // M2_4 |
| 121 | params->PcieRpTransmitterHalfSwing[24] = 1; // M2_2 |
| 122 | |
| 123 | params->CpuPcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // M2_1 |
| 124 | params->CpuPcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E1 |
| 125 | params->PcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // PCI_E2 |
| 126 | params->PcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E4 |
| 127 | params->PcieRpEnableCpm[4] = CONFIG(PCIEXP_CLK_PM); // PCI_E3 |
| 128 | params->PcieRpEnableCpm[8] = CONFIG(PCIEXP_CLK_PM); // M2_3 |
| 129 | params->PcieRpEnableCpm[20] = CONFIG(PCIEXP_CLK_PM); // M2_4 |
| 130 | params->PcieRpEnableCpm[24] = CONFIG(PCIEXP_CLK_PM); // M2_2 |
| 131 | |
| 132 | params->CpuPcieRpL1Substates[0] = aspm_l1; // M2_1 |
| 133 | params->CpuPcieRpL1Substates[1] = aspm_l1; // PCI_E1 |
| 134 | params->PcieRpL1Substates[0] = aspm_l1; // PCI_E2 |
| 135 | params->PcieRpL1Substates[1] = aspm_l1; // PCI_E4 |
| 136 | params->PcieRpL1Substates[4] = aspm_l1; // PCI_E3 |
| 137 | params->PcieRpL1Substates[8] = aspm_l1; // M2_3 |
| 138 | params->PcieRpL1Substates[20] = aspm_l1; // M2_4 |
| 139 | params->PcieRpL1Substates[24] = aspm_l1; // M2_2 |
| 140 | |
| 141 | params->CpuPcieRpAspm[0] = aspm; // M2_1 |
| 142 | params->CpuPcieRpAspm[1] = aspm; // PCI_E1 |
| 143 | params->PcieRpAspm[0] = aspm; // PCI_E2 |
| 144 | params->PcieRpAspm[1] = aspm; // PCI_E4 |
| 145 | params->PcieRpAspm[4] = aspm; // PCI_E3 |
| 146 | params->PcieRpAspm[8] = aspm; // M2_3 |
| 147 | params->PcieRpAspm[20] = aspm; // M2_4 |
| 148 | params->PcieRpAspm[24] = aspm; // M2_2 |
| 149 | |
| 150 | params->PcieRpAcsEnabled[0] = 1; // PCI_E2 |
| 151 | params->PcieRpAcsEnabled[1] = 1; // PCI_E4 |
| 152 | params->PcieRpAcsEnabled[2] = 1; // Ethernet |
| 153 | params->PcieRpAcsEnabled[4] = 1; // PCI_E3 |
| 154 | params->PcieRpAcsEnabled[8] = 1; // M2_3 |
| 155 | params->PcieRpAcsEnabled[20] = 1; // M2_4 |
| 156 | params->PcieRpAcsEnabled[24] = 1; // M2_2 |
| 157 | |
| 158 | params->CpuPcieClockGating[0] = CONFIG(PCIEXP_CLK_PM); |
| 159 | params->CpuPciePowerGating[0] = CONFIG(PCIEXP_CLK_PM); |
| 160 | params->CpuPcieRpMultiVcEnabled[0] = 1; |
| 161 | params->CpuPcieRpPeerToPeerMode[0] = 1; |
| 162 | params->CpuPcieRpMaxPayload[0] = 2; // 512B |
| 163 | params->CpuPcieRpAcsEnabled[0] = 1; |
| 164 | |
| 165 | params->CpuPcieClockGating[1] = CONFIG(PCIEXP_CLK_PM); |
| 166 | params->CpuPciePowerGating[1] = CONFIG(PCIEXP_CLK_PM); |
| 167 | params->CpuPcieRpPeerToPeerMode[1] = 1; |
| 168 | params->CpuPcieRpMaxPayload[1] = 2; // 512B |
| 169 | params->CpuPcieRpAcsEnabled[1] = 1; |
| 170 | |
| 171 | params->SataPortsSolidStateDrive[6] = 1; // M2_3 |
| 172 | params->SataPortsSolidStateDrive[7] = 1; // M2_4 |
| 173 | params->SataLedEnable = 1; |
| 174 | } |
| 175 | |
| 176 | #if CONFIG(GENERATE_SMBIOS_TABLES) |
| 177 | static const struct port_information smbios_type8_info[] = { |
| 178 | { |
| 179 | .internal_reference_designator = "PS2_USB1", |
| 180 | .internal_connector_type = CONN_NONE, |
| 181 | .external_reference_designator = "Keyboard", |
| 182 | .external_connector_type = CONN_PS_2, |
| 183 | .port_type = TYPE_KEYBOARD_PORT |
| 184 | }, |
| 185 | { |
| 186 | .internal_reference_designator = "PS2_USB1", |
| 187 | .internal_connector_type = CONN_NONE, |
| 188 | .external_reference_designator = "PS2Mouse", |
| 189 | .external_connector_type = CONN_PS_2, |
| 190 | .port_type = TYPE_MOUSE_PORT |
| 191 | }, |
| 192 | { |
| 193 | .internal_reference_designator = "PS2_USB1", |
| 194 | .internal_connector_type = CONN_NONE, |
| 195 | .external_reference_designator = "USB 2.0 Type-A", |
| 196 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 197 | .port_type = TYPE_USB |
| 198 | }, |
| 199 | { |
| 200 | .internal_reference_designator = "PS2_USB1", |
| 201 | .internal_connector_type = CONN_NONE, |
| 202 | .external_reference_designator = "USB 2.0 Type-A (Flash BIOS)", |
| 203 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 204 | .port_type = TYPE_USB |
| 205 | }, |
| 206 | { |
| 207 | .internal_reference_designator = "JTPM1 - TPM HDR", |
| 208 | .internal_connector_type = CONN_OTHER, |
| 209 | .external_reference_designator = "", |
| 210 | .external_connector_type = CONN_NONE, |
| 211 | .port_type = TYPE_OTHER_PORT |
| 212 | }, |
| 213 | { |
| 214 | .internal_reference_designator = "LAN_USB1", |
| 215 | .internal_connector_type = CONN_NONE, |
| 216 | .external_reference_designator = "Ethernet", |
| 217 | .external_connector_type = CONN_RJ_45, |
| 218 | .port_type = TYPE_NETWORK_PORT |
| 219 | }, |
| 220 | { |
| 221 | .internal_reference_designator = "LAN_USB1", |
| 222 | .internal_connector_type = CONN_NONE, |
| 223 | .external_reference_designator = "USB 3.2 Gen2x2 Type-C", |
| 224 | .external_connector_type = CONN_USB_TYPE_C, |
| 225 | .port_type = TYPE_USB |
| 226 | }, |
| 227 | { |
| 228 | .internal_reference_designator = "LAN_USB1", |
| 229 | .internal_connector_type = CONN_NONE, |
| 230 | .external_reference_designator = "USB 3.2 Gen2 Type-A", |
| 231 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 232 | .port_type = TYPE_USB |
| 233 | }, |
| 234 | { |
| 235 | .internal_reference_designator = "SATA1", |
| 236 | .internal_connector_type = CONN_SAS_SATA, |
| 237 | .external_reference_designator = "", |
| 238 | .external_connector_type = CONN_NONE, |
| 239 | .port_type = TYPE_SATA |
| 240 | }, |
| 241 | { |
| 242 | .internal_reference_designator = "SATA2", |
| 243 | .internal_connector_type = CONN_SAS_SATA, |
| 244 | .external_reference_designator = "", |
| 245 | .external_connector_type = CONN_NONE, |
| 246 | .port_type = TYPE_SATA |
| 247 | }, |
| 248 | { |
| 249 | .internal_reference_designator = "SATA3", |
| 250 | .internal_connector_type = CONN_SAS_SATA, |
| 251 | .external_reference_designator = "", |
| 252 | .external_connector_type = CONN_NONE, |
| 253 | .port_type = TYPE_SATA |
| 254 | }, |
| 255 | { |
| 256 | .internal_reference_designator = "SATA4", |
| 257 | .internal_connector_type = CONN_SAS_SATA, |
| 258 | .external_reference_designator = "", |
| 259 | .external_connector_type = CONN_NONE, |
| 260 | .port_type = TYPE_SATA |
| 261 | }, |
| 262 | { |
| 263 | .internal_reference_designator = "SATA5", |
| 264 | .internal_connector_type = CONN_SAS_SATA, |
| 265 | .external_reference_designator = "", |
| 266 | .external_connector_type = CONN_NONE, |
| 267 | .port_type = TYPE_SATA |
| 268 | }, |
| 269 | { |
| 270 | .internal_reference_designator = "SATA6", |
| 271 | .internal_connector_type = CONN_SAS_SATA, |
| 272 | .external_reference_designator = "", |
| 273 | .external_connector_type = CONN_NONE, |
| 274 | .port_type = TYPE_SATA |
| 275 | }, |
| 276 | { |
| 277 | .internal_reference_designator = "JTBT1", |
| 278 | .internal_connector_type = CONN_OTHER, |
| 279 | .external_reference_designator = "", |
| 280 | .external_connector_type = CONN_NONE, |
| 281 | .port_type = TYPE_THUNDERBOLT |
| 282 | }, |
| 283 | { |
| 284 | .internal_reference_designator = "JC1 - CHASSIS INTRUSION", |
| 285 | .internal_connector_type = CONN_OTHER, |
| 286 | .external_reference_designator = "", |
| 287 | .external_connector_type = CONN_NONE, |
| 288 | .port_type = TYPE_OTHER_PORT |
| 289 | }, |
| 290 | { |
| 291 | .internal_reference_designator = "JAUD1 - FRONT AUDIO", |
| 292 | .internal_connector_type = CONN_OTHER, |
| 293 | .external_reference_designator = "", |
| 294 | .external_connector_type = CONN_NONE, |
| 295 | .port_type = TYPE_AUDIO_PORT |
| 296 | }, |
| 297 | { |
| 298 | .internal_reference_designator = "AUDIO1 - REAR AUDIO", |
| 299 | .internal_connector_type = CONN_NONE, |
| 300 | .external_reference_designator = "Audio", |
| 301 | .external_connector_type = CONN_OTHER, |
| 302 | .port_type = TYPE_AUDIO_PORT |
| 303 | }, |
| 304 | { |
| 305 | .internal_reference_designator = "JFP1 - FRONT PANEL", |
| 306 | .internal_connector_type = CONN_OTHER, |
| 307 | .external_reference_designator = "", |
| 308 | .external_connector_type = CONN_NONE, |
| 309 | .port_type = TYPE_OTHER_PORT |
| 310 | }, |
| 311 | { |
| 312 | .internal_reference_designator = "JFP2 - PC SPEAKER", |
| 313 | .internal_connector_type = CONN_OTHER, |
| 314 | .external_reference_designator = "", |
| 315 | .external_connector_type = CONN_NONE, |
| 316 | .port_type = TYPE_OTHER_PORT |
| 317 | }, |
| 318 | { |
| 319 | .internal_reference_designator = "JBAT1 - CLEAR CMOS", |
| 320 | .internal_connector_type = CONN_OTHER, |
| 321 | .external_reference_designator = "", |
| 322 | .external_connector_type = CONN_NONE, |
| 323 | .port_type = TYPE_OTHER_PORT |
| 324 | }, |
| 325 | { |
| 326 | .internal_reference_designator = "JDASH1 - TUNING CONTROLLER", |
| 327 | .internal_connector_type = CONN_OTHER, |
| 328 | .external_reference_designator = "", |
| 329 | .external_connector_type = CONN_NONE, |
| 330 | .port_type = TYPE_OTHER_PORT |
| 331 | }, |
| 332 | { |
| 333 | .internal_reference_designator = "JRGB1 - 5050 RGB LED", |
| 334 | .internal_connector_type = CONN_OTHER, |
| 335 | .external_reference_designator = "", |
| 336 | .external_connector_type = CONN_NONE, |
| 337 | .port_type = TYPE_OTHER_PORT |
| 338 | }, |
| 339 | { |
| 340 | .internal_reference_designator = "JRAINBOW1 - WS2812B RGB LED", |
| 341 | .internal_connector_type = CONN_OTHER, |
| 342 | .external_reference_designator = "", |
| 343 | .external_connector_type = CONN_NONE, |
| 344 | .port_type = TYPE_OTHER_PORT |
| 345 | }, |
| 346 | { |
| 347 | .internal_reference_designator = "JRAINBOW2 - WS2812B RGB LED", |
| 348 | .internal_connector_type = CONN_OTHER, |
| 349 | .external_reference_designator = "", |
| 350 | .external_connector_type = CONN_NONE, |
| 351 | .port_type = TYPE_OTHER_PORT |
| 352 | }, |
| 353 | { |
| 354 | .internal_reference_designator = "CPU_FAN1", |
| 355 | .internal_connector_type = CONN_OTHER, |
| 356 | .external_reference_designator = "", |
| 357 | .external_connector_type = CONN_NONE, |
| 358 | .port_type = TYPE_OTHER_PORT |
| 359 | }, |
| 360 | { |
| 361 | .internal_reference_designator = "PUMP_FAN1", |
| 362 | .internal_connector_type = CONN_OTHER, |
| 363 | .external_reference_designator = "", |
| 364 | .external_connector_type = CONN_NONE, |
| 365 | .port_type = TYPE_OTHER_PORT |
| 366 | }, |
| 367 | { |
| 368 | .internal_reference_designator = "SYS_FAN1", |
| 369 | .internal_connector_type = CONN_OTHER, |
| 370 | .external_reference_designator = "", |
| 371 | .external_connector_type = CONN_NONE, |
| 372 | .port_type = TYPE_OTHER_PORT |
| 373 | }, |
| 374 | { |
| 375 | .internal_reference_designator = "SYS_FAN2", |
| 376 | .internal_connector_type = CONN_OTHER, |
| 377 | .external_reference_designator = "", |
| 378 | .external_connector_type = CONN_NONE, |
| 379 | .port_type = TYPE_OTHER_PORT |
| 380 | }, |
| 381 | { |
| 382 | .internal_reference_designator = "SYS_FAN3", |
| 383 | .internal_connector_type = CONN_OTHER, |
| 384 | .external_reference_designator = "", |
| 385 | .external_connector_type = CONN_NONE, |
| 386 | .port_type = TYPE_OTHER_PORT |
| 387 | }, |
| 388 | { |
| 389 | .internal_reference_designator = "SYS_FAN4", |
| 390 | .internal_connector_type = CONN_OTHER, |
| 391 | .external_reference_designator = "", |
| 392 | .external_connector_type = CONN_NONE, |
| 393 | .port_type = TYPE_OTHER_PORT |
| 394 | }, |
| 395 | { |
| 396 | .internal_reference_designator = "SYS_FAN5", |
| 397 | .internal_connector_type = CONN_OTHER, |
| 398 | .external_reference_designator = "", |
| 399 | .external_connector_type = CONN_NONE, |
| 400 | .port_type = TYPE_OTHER_PORT |
| 401 | }, |
| 402 | { |
| 403 | .internal_reference_designator = "SYS_FAN6", |
| 404 | .internal_connector_type = CONN_OTHER, |
| 405 | .external_reference_designator = "", |
| 406 | .external_connector_type = CONN_NONE, |
| 407 | .port_type = TYPE_OTHER_PORT |
| 408 | }, |
| 409 | { |
| 410 | .internal_reference_designator = "DP_HDMI1", |
| 411 | .internal_connector_type = CONN_NONE, |
| 412 | .external_reference_designator = "HDMI", |
| 413 | .external_connector_type = CONN_OTHER, |
| 414 | .port_type = TYPE_VIDEO_PORT |
| 415 | }, |
| 416 | { |
| 417 | .internal_reference_designator = "DP_HDMI1", |
| 418 | .internal_connector_type = CONN_NONE, |
| 419 | .external_reference_designator = "Display Port", |
| 420 | .external_connector_type = CONN_OTHER, |
| 421 | .port_type = TYPE_VIDEO_PORT |
| 422 | }, |
| 423 | { |
| 424 | .internal_reference_designator = "USB2", |
| 425 | .internal_connector_type = CONN_NONE, |
| 426 | .external_reference_designator = "USB 2.0 Type-A (Upper)", |
| 427 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 428 | .port_type = TYPE_USB |
| 429 | }, |
| 430 | { |
| 431 | .internal_reference_designator = "USB2", |
| 432 | .internal_connector_type = CONN_NONE, |
| 433 | .external_reference_designator = "USB 2.0 Type-A (Lower)", |
| 434 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 435 | .port_type = TYPE_USB |
| 436 | }, |
| 437 | { |
| 438 | .internal_reference_designator = "USB2", |
| 439 | .internal_connector_type = CONN_NONE, |
| 440 | .external_reference_designator = "USB 3.2 Gen1 Type-A (Upper)", |
| 441 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 442 | .port_type = TYPE_USB |
| 443 | }, |
| 444 | { |
| 445 | .internal_reference_designator = "USB2", |
| 446 | .internal_connector_type = CONN_NONE, |
| 447 | .external_reference_designator = "USB 3.2 Gen1 Type-A (Lower)", |
| 448 | .external_connector_type = CONN_ACCESS_BUS_USB, |
| 449 | .port_type = TYPE_USB |
| 450 | }, |
| 451 | { |
| 452 | .internal_reference_designator = "JUSB1 - USB 2.0 ", |
| 453 | .internal_connector_type = CONN_OTHER, |
| 454 | .external_reference_designator = "", |
| 455 | .external_connector_type = CONN_NONE, |
| 456 | .port_type = TYPE_USB |
| 457 | }, |
| 458 | { |
| 459 | .internal_reference_designator = "JUSB2 - USB 2.0", |
| 460 | .internal_connector_type = CONN_OTHER, |
| 461 | .external_reference_designator = "", |
| 462 | .external_connector_type = CONN_NONE, |
| 463 | .port_type = TYPE_USB |
| 464 | }, |
| 465 | { |
| 466 | .internal_reference_designator = "JUSB3 - USB 3.2 GEN 1", |
| 467 | .internal_connector_type = CONN_OTHER, |
| 468 | .external_reference_designator = "", |
| 469 | .external_connector_type = CONN_NONE, |
| 470 | .port_type = TYPE_USB |
| 471 | }, |
| 472 | { |
| 473 | .internal_reference_designator = "JUSB4 - USB 3.2 GEN 1", |
| 474 | .internal_connector_type = CONN_OTHER, |
| 475 | .external_reference_designator = "", |
| 476 | .external_connector_type = CONN_NONE, |
| 477 | .port_type = TYPE_USB |
| 478 | }, |
| 479 | { |
| 480 | .internal_reference_designator = "JUSB5 - USB-C", |
| 481 | .internal_connector_type = CONN_OTHER, |
| 482 | .external_reference_designator = "", |
| 483 | .external_connector_type = CONN_NONE, |
| 484 | .port_type = TYPE_USB |
| 485 | }, |
| 486 | { |
| 487 | .internal_reference_designator = "ATX_PWR1", |
| 488 | .internal_connector_type = CONN_OTHER, |
| 489 | .external_reference_designator = "", |
| 490 | .external_connector_type = CONN_NONE, |
| 491 | .port_type = TYPE_OTHER_PORT |
| 492 | }, |
| 493 | { |
| 494 | .internal_reference_designator = "CPU_PWR1", |
| 495 | .internal_connector_type = CONN_OTHER, |
| 496 | .external_reference_designator = "", |
| 497 | .external_connector_type = CONN_NONE, |
| 498 | .port_type = TYPE_OTHER_PORT |
| 499 | }, |
| 500 | { |
| 501 | .internal_reference_designator = "CPU_PWR2", |
| 502 | .internal_connector_type = CONN_OTHER, |
| 503 | .external_reference_designator = "", |
| 504 | .external_connector_type = CONN_NONE, |
| 505 | .port_type = TYPE_OTHER_PORT |
| 506 | }, |
| 507 | }; |
| 508 | |
| 509 | static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) |
| 510 | { |
| 511 | int len = 0; |
| 512 | |
| 513 | // add port information |
| 514 | len += smbios_write_type8( |
| 515 | current, handle, |
| 516 | smbios_type8_info, |
| 517 | ARRAY_SIZE(smbios_type8_info) |
| 518 | ); |
| 519 | |
| 520 | return len; |
| 521 | } |
| 522 | #endif |
| 523 | |
| 524 | static void mainboard_enable(struct device *dev) |
| 525 | { |
| 526 | #if CONFIG(GENERATE_SMBIOS_TABLES) |
| 527 | dev->ops->get_smbios_data = mainboard_smbios_data; |
| 528 | #endif |
| 529 | } |
| 530 | |
| 531 | struct chip_operations mainboard_ops = { |
| 532 | .init = mainboard_init, |
| 533 | .enable_dev = mainboard_enable, |
| 534 | }; |