blob: 57de4b82fb2126df685d265724289893324936b2 [file] [log] [blame]
Subrata Banik208587e2017-05-19 18:38:24 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Intel Corp.
5 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
6 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
Pratik Prajapati73841452017-08-28 15:11:49 -070019#include <cpu/cpu.h>
20#include <console/console.h>
Subrata Banik208587e2017-05-19 18:38:24 +053021#include <device/device.h>
Pratik Prajapati73841452017-08-28 15:11:49 -070022#include <fsp/util.h>
Subrata Banik208587e2017-05-19 18:38:24 +053023#include <intelblocks/systemagent.h>
24#include <soc/iomap.h>
25#include <soc/systemagent.h>
26
27/*
28 * SoC implementation
29 *
30 * Add all known fixed memory ranges for Host Controller/Mmeory
31 * controller.
32 */
33void soc_add_fixed_mmio_resources(struct device *dev, int *index)
34{
35 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
36 { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
37 "PCIEXBAR" },
38 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
39 };
40
41 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
42 ARRAY_SIZE(soc_fixed_resources));
43}
Pratik Prajapati73841452017-08-28 15:11:49 -070044
45int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
46 uint64_t *prmrr_mask)
47{
48 const void *hob;
49 size_t hob_size, prmrr_size;
50 uint64_t phys_address_mask;
51 const uint8_t prmrr_phys_base_guid[16] = {
52 0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f,
53 0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33
54 };
55 const uint8_t prmrr_size_guid[16] = {
56 0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42,
57 0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41
58 };
59
60 hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid,
61 &hob_size);
62 if (!hob) {
63 printk(BIOS_ERR, "Failed to locate PRMRR base hob\n");
64 return -1;
65 }
66 if (hob_size != sizeof(uint64_t)) {
67 printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
68 return -1;
69 }
70 *prmrr_base = *(uint64_t *) hob;
71
72 hob = fsp_find_extension_hob_by_guid(prmrr_size_guid,
73 &hob_size);
74 if (!hob) {
75 printk(BIOS_ERR, "Failed to locate PRMRR size hob\n");
76 return -1;
77 }
78 if (hob_size != sizeof(uint64_t)) {
79 printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
80 return -1;
81 }
82 prmrr_size = *(uint64_t *) hob;
83 phys_address_mask = (1ULL << cpu_phys_address_size()) - 1;
84 *prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1);
85
86 return 0;
87}