Angel Pons | b6636b0 | 2020-04-05 13:21:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 2 | |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
Edward O'Callaghan | d516656 | 2020-02-20 13:46:38 +1100 | [diff] [blame] | 6 | #include <ec/google/chromeec/ec.h> |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 7 | |
David Wu | 460a175 | 2019-08-13 09:49:48 +0800 | [diff] [blame] | 8 | static const struct pad_config ssd_sku_gpio_table[] = { |
Edward O'Callaghan | c4a3f51 | 2019-12-24 14:11:43 +1100 | [diff] [blame] | 9 | /* A0 : SAR0_INT_ODL */ |
| 10 | PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), |
| 11 | /* A6 : SAR1_INT_ODL */ |
| 12 | PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), |
| 13 | /* A8 : PEN_GARAGE_DET_L (wake) */ |
| 14 | PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), |
| 15 | /* A10 : FPMCU_PCH_BOOT1 */ |
| 16 | PAD_CFG_GPO(GPP_A10, 0, DEEP), |
| 17 | /* A11 : PCH_SPI_FPMCU_CS_L */ |
| 18 | PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), |
| 19 | /* A12 : FPMCU_RST_ODL */ |
| 20 | PAD_CFG_GPO(GPP_A12, 0, DEEP), |
Edward O'Callaghan | 3dbe593 | 2019-12-24 15:15:35 +1100 | [diff] [blame] | 21 | /* C15 : WWAN_DPR_SAR_ODL |
| 22 | * |
| 23 | * TODO: Driver doesn't use this pin as of now. In case driver starts |
| 24 | * using this pin, expose this pin to driver. |
| 25 | */ |
| 26 | PAD_CFG_GPO(GPP_C15, 1, DEEP), |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 27 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 28 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 29 | /* D15 : TOUCHSCREEN_RST_L */ |
| 30 | PAD_CFG_GPO(GPP_D15, 1, DEEP), |
David Wu | 460a175 | 2019-08-13 09:49:48 +0800 | [diff] [blame] | 31 | /* F3 : MEM_STRAP_3 */ |
| 32 | PAD_CFG_GPI(GPP_F3, NONE, PLTRST), |
| 33 | /* F10 : MEM_STRAP_2 */ |
| 34 | PAD_CFG_GPI(GPP_F10, NONE, PLTRST), |
| 35 | /* F11 : EMMC_CMD ==> NC */ |
| 36 | PAD_NC(GPP_F11, NONE), |
| 37 | /* F12 : EMMC_DATA0 ==> NC */ |
| 38 | PAD_NC(GPP_F12, NONE), |
| 39 | /* F13 : EMMC_DATA1 ==> NC */ |
| 40 | PAD_NC(GPP_F13, NONE), |
| 41 | /* F14 : EMMC_DATA2 ==> NC */ |
| 42 | PAD_NC(GPP_F14, NONE), |
| 43 | /* F15 : EMMC_DATA3 ==> NC */ |
| 44 | PAD_NC(GPP_F15, NONE), |
| 45 | /* F16 : EMMC_DATA4 ==> NC */ |
| 46 | PAD_NC(GPP_F16, NONE), |
| 47 | /* F17 : EMMC_DATA5 ==> NC */ |
| 48 | PAD_NC(GPP_F17, NONE), |
| 49 | /* F18 : EMMC_DATA6 ==> NC */ |
| 50 | PAD_NC(GPP_F18, NONE), |
| 51 | /* F19 : EMMC_DATA7 ==> NC */ |
| 52 | PAD_NC(GPP_F19, NONE), |
| 53 | /* F20 : EMMC_RCLK ==> NC */ |
| 54 | PAD_NC(GPP_F20, NONE), |
| 55 | /* F21 : EMMC_CLK ==> NC */ |
| 56 | PAD_NC(GPP_F21, NONE), |
| 57 | /* F22 : EMMC_RESET# ==> NC */ |
| 58 | PAD_NC(GPP_F22, NONE), |
Edward O'Callaghan | c735a31 | 2019-12-24 15:35:44 +1100 | [diff] [blame] | 59 | /* H3 : SPKR_PA_EN */ |
| 60 | PAD_CFG_GPO(GPP_H3, 0, DEEP), |
David Wu | 460a175 | 2019-08-13 09:49:48 +0800 | [diff] [blame] | 61 | /* H19 : MEM_STRAP_0 */ |
| 62 | PAD_CFG_GPI(GPP_H19, NONE, PLTRST), |
| 63 | /* H22 : MEM_STRAP_1 */ |
| 64 | PAD_CFG_GPI(GPP_H22, NONE, PLTRST), |
| 65 | }; |
| 66 | |
David Wu | 434a975 | 2019-08-08 19:20:55 +0800 | [diff] [blame] | 67 | static const struct pad_config emmc_sku_gpio_table[] = { |
Edward O'Callaghan | c4a3f51 | 2019-12-24 14:11:43 +1100 | [diff] [blame] | 68 | /* A0 : SAR0_INT_ODL */ |
| 69 | PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), |
| 70 | /* A6 : SAR1_INT_ODL */ |
| 71 | PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), |
| 72 | /* A8 : PEN_GARAGE_DET_L (wake) */ |
| 73 | PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), |
| 74 | /* A10 : FPMCU_PCH_BOOT1 */ |
| 75 | PAD_CFG_GPO(GPP_A10, 0, DEEP), |
| 76 | /* A11 : PCH_SPI_FPMCU_CS_L */ |
| 77 | PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), |
| 78 | /* A12 : FPMCU_RST_ODL */ |
| 79 | PAD_CFG_GPO(GPP_A12, 0, DEEP), |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 80 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 81 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 82 | /* D15 : TOUCHSCREEN_RST_L */ |
| 83 | PAD_CFG_GPO(GPP_D15, 1, DEEP), |
David Wu | 434a975 | 2019-08-08 19:20:55 +0800 | [diff] [blame] | 84 | /* E1 : M2_SSD_PEDET ==> NC */ |
| 85 | PAD_NC(GPP_E1, NONE), |
| 86 | /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ |
| 87 | PAD_NC(GPP_E4, NONE), |
| 88 | /* E5 : SATA_DEVSLP1 ==> NC */ |
| 89 | PAD_NC(GPP_E5, NONE), |
Edward O'Callaghan | 3dbe593 | 2019-12-24 15:15:35 +1100 | [diff] [blame] | 90 | /* C15 : WWAN_DPR_SAR_ODL |
| 91 | * |
| 92 | * TODO: Driver doesn't use this pin as of now. In case driver starts |
| 93 | * using this pin, expose this pin to driver. |
| 94 | */ |
| 95 | PAD_CFG_GPO(GPP_C15, 1, DEEP), |
David Wu | 434a975 | 2019-08-08 19:20:55 +0800 | [diff] [blame] | 96 | /* F3 : MEM_STRAP_3 */ |
| 97 | PAD_CFG_GPI(GPP_F3, NONE, PLTRST), |
| 98 | /* F10 : MEM_STRAP_2 */ |
| 99 | PAD_CFG_GPI(GPP_F10, NONE, PLTRST), |
| 100 | /* F11 : EMMC_CMD ==> EMMC_CMD */ |
| 101 | PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), |
| 102 | /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ |
| 103 | PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), |
| 104 | /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ |
| 105 | PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), |
| 106 | /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ |
| 107 | PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), |
| 108 | /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ |
| 109 | PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), |
| 110 | /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ |
| 111 | PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), |
| 112 | /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ |
| 113 | PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), |
| 114 | /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ |
| 115 | PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), |
| 116 | /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ |
| 117 | PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |
| 118 | /* F20 : EMMC_RCLK ==> EMMC_RCLK */ |
| 119 | PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), |
| 120 | /* F21 : EMMC_CLK ==> EMMC_CLK */ |
| 121 | PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), |
| 122 | /* F22 : EMMC_RESET# ==> EMMC_RST_L */ |
| 123 | PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), |
Edward O'Callaghan | c735a31 | 2019-12-24 15:35:44 +1100 | [diff] [blame] | 124 | /* H3 : SPKR_PA_EN */ |
| 125 | PAD_CFG_GPO(GPP_H3, 0, DEEP), |
David Wu | 434a975 | 2019-08-08 19:20:55 +0800 | [diff] [blame] | 126 | /* H19 : MEM_STRAP_0 */ |
| 127 | PAD_CFG_GPI(GPP_H19, NONE, PLTRST), |
| 128 | /* H22 : MEM_STRAP_1 */ |
| 129 | PAD_CFG_GPI(GPP_H22, NONE, PLTRST), |
| 130 | }; |
| 131 | |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 132 | static const struct pad_config gpio_table[] = { |
Edward O'Callaghan | c4a3f51 | 2019-12-24 14:11:43 +1100 | [diff] [blame] | 133 | /* A0 : SAR0_INT_ODL */ |
| 134 | PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), |
| 135 | /* A6 : SAR1_INT_ODL */ |
| 136 | PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), |
| 137 | /* A8 : PEN_GARAGE_DET_L (wake) */ |
| 138 | PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), |
| 139 | /* A10 : FPMCU_PCH_BOOT1 */ |
| 140 | PAD_CFG_GPO(GPP_A10, 0, DEEP), |
| 141 | /* A11 : PCH_SPI_FPMCU_CS_L */ |
| 142 | PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), |
| 143 | /* A12 : FPMCU_RST_ODL */ |
| 144 | PAD_CFG_GPO(GPP_A12, 0, DEEP), |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 145 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 146 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 147 | /* D15 : TOUCHSCREEN_RST_L */ |
| 148 | PAD_CFG_GPO(GPP_D15, 1, DEEP), |
Edward O'Callaghan | 3dbe593 | 2019-12-24 15:15:35 +1100 | [diff] [blame] | 149 | /* C15 : WWAN_DPR_SAR_ODL |
| 150 | * |
| 151 | * TODO: Driver doesn't use this pin as of now. In case driver starts |
| 152 | * using this pin, expose this pin to driver. |
| 153 | */ |
| 154 | PAD_CFG_GPO(GPP_C15, 1, DEEP), |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 155 | /* F3 : MEM_STRAP_3 */ |
| 156 | PAD_CFG_GPI(GPP_F3, NONE, PLTRST), |
| 157 | /* F10 : MEM_STRAP_2 */ |
| 158 | PAD_CFG_GPI(GPP_F10, NONE, PLTRST), |
David Wu | 21f1ccc | 2019-06-19 20:09:17 +0800 | [diff] [blame] | 159 | /* F11 : EMMC_CMD ==> EMMC_CMD */ |
| 160 | PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), |
| 161 | /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ |
| 162 | PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), |
| 163 | /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ |
| 164 | PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), |
| 165 | /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ |
| 166 | PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), |
| 167 | /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ |
| 168 | PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), |
| 169 | /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ |
| 170 | PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), |
| 171 | /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ |
| 172 | PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), |
| 173 | /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ |
| 174 | PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), |
| 175 | /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ |
| 176 | PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |
| 177 | /* F20 : EMMC_RCLK ==> EMMC_RCLK */ |
| 178 | PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), |
| 179 | /* F21 : EMMC_CLK ==> EMMC_CLK */ |
| 180 | PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), |
| 181 | /* F22 : EMMC_RESET# ==> EMMC_RST_L */ |
| 182 | PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), |
Edward O'Callaghan | c735a31 | 2019-12-24 15:35:44 +1100 | [diff] [blame] | 183 | /* H3 : SPKR_PA_EN */ |
| 184 | PAD_CFG_GPO(GPP_H3, 0, DEEP), |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 185 | /* H19 : MEM_STRAP_0 */ |
| 186 | PAD_CFG_GPI(GPP_H19, NONE, PLTRST), |
| 187 | /* H22 : MEM_STRAP_1 */ |
| 188 | PAD_CFG_GPI(GPP_H22, NONE, PLTRST), |
| 189 | }; |
| 190 | |
| 191 | const struct pad_config *override_gpio_table(size_t *num) |
| 192 | { |
Edward O'Callaghan | d516656 | 2020-02-20 13:46:38 +1100 | [diff] [blame] | 193 | uint32_t sku_id = google_chromeec_get_board_sku(); |
David Wu | 460a175 | 2019-08-13 09:49:48 +0800 | [diff] [blame] | 194 | /* For SSD SKU */ |
| 195 | if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { |
| 196 | *num = ARRAY_SIZE(ssd_sku_gpio_table); |
| 197 | return ssd_sku_gpio_table; |
| 198 | } |
David Wu | 434a975 | 2019-08-08 19:20:55 +0800 | [diff] [blame] | 199 | /* For eMMC SKU */ |
| 200 | if (sku_id == 2 || sku_id == 4 || sku_id == 21 || sku_id == 22) { |
| 201 | *num = ARRAY_SIZE(emmc_sku_gpio_table); |
| 202 | return emmc_sku_gpio_table; |
| 203 | } |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 204 | *num = ARRAY_SIZE(gpio_table); |
| 205 | return gpio_table; |
| 206 | } |
| 207 | |
Tim Wawrzynczak | 08eca5d | 2019-08-07 15:33:04 -0600 | [diff] [blame] | 208 | /* |
| 209 | * GPIOs configured before ramstage |
| 210 | * Note: the Hatch platform's romstage will configure |
| 211 | * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins |
| 212 | * as inputs before it reads them, so they are not |
| 213 | * needed in this table. |
| 214 | */ |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 215 | static const struct pad_config early_gpio_table[] = { |
Tim Wawrzynczak | 08eca5d | 2019-08-07 15:33:04 -0600 | [diff] [blame] | 216 | /* B15 : H1_SLAVE_SPI_CS_L */ |
| 217 | PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |
| 218 | /* B16 : H1_SLAVE_SPI_CLK */ |
| 219 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), |
| 220 | /* B17 : H1_SLAVE_SPI_MISO_R */ |
| 221 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), |
| 222 | /* B18 : H1_SLAVE_SPI_MOSI_R */ |
| 223 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), |
Michael Niewöhner | 3a2d400 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 224 | /* C8 : UART_PCH_RX_DEBUG_TX */ |
| 225 | PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), |
| 226 | /* C9 : UART_PCH_TX_DEBUG_RX */ |
| 227 | PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), |
Tim Wawrzynczak | 08eca5d | 2019-08-07 15:33:04 -0600 | [diff] [blame] | 228 | /* C14 : BT_DISABLE_L */ |
| 229 | PAD_CFG_GPO(GPP_C14, 0, DEEP), |
| 230 | /* PCH_WP_OD */ |
| 231 | PAD_CFG_GPI(GPP_C20, NONE, DEEP), |
| 232 | /* C21 : H1_PCH_INT_ODL */ |
| 233 | PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 234 | /* C22 : EC_IN_RW_OD */ |
| 235 | PAD_CFG_GPI(GPP_C22, NONE, DEEP), |
Tim Wawrzynczak | 08eca5d | 2019-08-07 15:33:04 -0600 | [diff] [blame] | 236 | /* C23 : WLAN_PE_RST# */ |
| 237 | PAD_CFG_GPO(GPP_C23, 1, DEEP), |
| 238 | /* E1 : M2_SSD_PEDET */ |
| 239 | PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), |
| 240 | /* E5 : SATA_DEVSLP1 */ |
| 241 | PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), |
| 242 | /* F2 : MEM_CH_SEL */ |
| 243 | PAD_CFG_GPI(GPP_F2, NONE, PLTRST), |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 244 | }; |
| 245 | |
Tim Wawrzynczak | 08eca5d | 2019-08-07 15:33:04 -0600 | [diff] [blame] | 246 | const struct pad_config *variant_early_gpio_table(size_t *num) |
David Wu | 493d366 | 2019-06-19 19:46:37 +0800 | [diff] [blame] | 247 | { |
| 248 | *num = ARRAY_SIZE(early_gpio_table); |
| 249 | return early_gpio_table; |
| 250 | } |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 251 | |
| 252 | /* GPIOs needed to be set in romstage. */ |
| 253 | static const struct pad_config romstage_gpio_table[] = { |
| 254 | /* Enable touchscreen, hold in reset */ |
| 255 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 256 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 257 | /* D15 : TOUCHSCREEN_RST_L */ |
| 258 | PAD_CFG_GPO(GPP_D15, 0, DEEP), |
| 259 | }; |
| 260 | |
| 261 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 262 | { |
| 263 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 264 | return romstage_gpio_table; |
| 265 | } |