Angel Pons | b6636b0 | 2020-04-05 13:21:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 4 | #include <baseboard/gpio.h> |
| 5 | #include <baseboard/variants.h> |
| 6 | #include <commonlib/helpers.h> |
| 7 | |
| 8 | static const struct pad_config gpio_table[] = { |
Edward O'Callaghan | c4a3f51 | 2019-12-24 14:11:43 +1100 | [diff] [blame] | 9 | /* A11 : PCH_SPI_FPMCU_CS_L */ |
| 10 | PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), |
| 11 | /* A12 : FPMCU_RST_ODL */ |
| 12 | PAD_CFG_GPO(GPP_A12, 0, DEEP), |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 13 | /* C12 : FPMCU_PCH_BOOT1 */ |
| 14 | PAD_CFG_GPO(GPP_C12, 0, DEEP), |
Edward O'Callaghan | 3dbe593 | 2019-12-24 15:15:35 +1100 | [diff] [blame] | 15 | /* C15 : WWAN_DPR_SAR_ODL |
| 16 | * |
| 17 | * TODO: Driver doesn't use this pin as of now. In case driver starts |
| 18 | * using this pin, expose this pin to driver. |
| 19 | */ |
| 20 | PAD_CFG_GPO(GPP_C15, 1, DEEP), |
Ricardo Ribalda | 43d0a7e | 2020-10-05 12:53:46 +0000 | [diff] [blame] | 21 | /* D4 : Camera Privacy Status */ |
| 22 | PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 23 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 24 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 25 | /* D15 : TOUCHSCREEN_RST_L */ |
| 26 | PAD_CFG_GPO(GPP_D15, 1, DEEP), |
Rajat Jain | a5f8b8c | 2020-02-26 11:15:49 -0800 | [diff] [blame] | 27 | /* E0 : View Angle Management */ |
| 28 | PAD_CFG_GPO(GPP_E0, 0, DEEP), |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 29 | /* F3 : MEM_STRAP_3 */ |
| 30 | PAD_CFG_GPI(GPP_F3, NONE, PLTRST), |
| 31 | /* F10 : MEM_STRAP_2 */ |
| 32 | PAD_CFG_GPI(GPP_F10, NONE, PLTRST), |
| 33 | /* F11 : EMMC_CMD ==> NC */ |
| 34 | PAD_NC(GPP_F11, NONE), |
| 35 | /* F12 : EMMC_DATA0 ==> NC */ |
| 36 | PAD_NC(GPP_F12, NONE), |
| 37 | /* F13 : EMMC_DATA1 ==> NC */ |
| 38 | PAD_NC(GPP_F13, NONE), |
| 39 | /* F14 : EMMC_DATA2 ==> NC */ |
| 40 | PAD_NC(GPP_F14, NONE), |
| 41 | /* F15 : EMMC_DATA3 ==> NC */ |
| 42 | PAD_NC(GPP_F15, NONE), |
| 43 | /* F16 : EMMC_DATA4 ==> NC */ |
| 44 | PAD_NC(GPP_F16, NONE), |
| 45 | /* F17 : EMMC_DATA5 ==> NC */ |
| 46 | PAD_NC(GPP_F17, NONE), |
| 47 | /* F18 : EMMC_DATA6 ==> NC */ |
| 48 | PAD_NC(GPP_F18, NONE), |
| 49 | /* F19 : EMMC_DATA7 ==> NC */ |
| 50 | PAD_NC(GPP_F19, NONE), |
| 51 | /* F20 : EMMC_RCLK ==> NC */ |
| 52 | PAD_NC(GPP_F20, NONE), |
| 53 | /* F21 : EMMC_CLK ==> NC */ |
| 54 | PAD_NC(GPP_F21, NONE), |
| 55 | /* F22 : EMMC_RESET# ==> NC */ |
| 56 | PAD_NC(GPP_F22, NONE), |
Edward O'Callaghan | c735a31 | 2019-12-24 15:35:44 +1100 | [diff] [blame] | 57 | /* H3 : SPKR_PA_EN */ |
| 58 | PAD_CFG_GPO(GPP_H3, 0, DEEP), |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 59 | /* H19 : MEM_STRAP_0 */ |
| 60 | PAD_CFG_GPI(GPP_H19, NONE, PLTRST), |
| 61 | /* H22 : MEM_STRAP_1 */ |
| 62 | PAD_CFG_GPI(GPP_H22, NONE, PLTRST), |
| 63 | }; |
| 64 | |
| 65 | const struct pad_config *override_gpio_table(size_t *num) |
| 66 | { |
| 67 | *num = ARRAY_SIZE(gpio_table); |
| 68 | return gpio_table; |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * GPIOs configured before ramstage |
| 73 | * Note: the Hatch platform's romstage will configure |
| 74 | * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins |
| 75 | * as inputs before it reads them, so they are not |
| 76 | * needed in this table. |
| 77 | */ |
| 78 | static const struct pad_config early_gpio_table[] = { |
| 79 | /* B15 : H1_SLAVE_SPI_CS_L */ |
| 80 | PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |
| 81 | /* B16 : H1_SLAVE_SPI_CLK */ |
| 82 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), |
| 83 | /* B17 : H1_SLAVE_SPI_MISO_R */ |
| 84 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), |
| 85 | /* B18 : H1_SLAVE_SPI_MOSI_R */ |
| 86 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), |
Michael Niewöhner | 3a2d400 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 87 | /* C8 : UART_PCH_RX_DEBUG_TX */ |
| 88 | PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), |
| 89 | /* C9 : UART_PCH_TX_DEBUG_RX */ |
| 90 | PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 91 | /* C14 : BT_DISABLE_L */ |
| 92 | PAD_CFG_GPO(GPP_C14, 0, DEEP), |
| 93 | /* PCH_WP_OD */ |
| 94 | PAD_CFG_GPI(GPP_C20, NONE, DEEP), |
| 95 | /* C21 : H1_PCH_INT_ODL */ |
| 96 | PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), |
Hsuan-ting Chen | 642508a | 2021-10-27 10:59:41 +0000 | [diff] [blame] | 97 | /* C22 : EC_IN_RW_OD */ |
| 98 | PAD_CFG_GPI(GPP_C22, NONE, DEEP), |
Wisley Chen | 3bc7022 | 2019-11-08 23:51:00 +0800 | [diff] [blame] | 99 | /* C23 : WLAN_PE_RST# */ |
| 100 | PAD_CFG_GPO(GPP_C23, 1, DEEP), |
| 101 | /* E1 : M2_SSD_PEDET */ |
| 102 | PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), |
| 103 | /* E5 : SATA_DEVSLP1 */ |
| 104 | PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), |
| 105 | /* F2 : MEM_CH_SEL */ |
| 106 | PAD_CFG_GPI(GPP_F2, NONE, PLTRST), |
| 107 | }; |
| 108 | |
| 109 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 110 | { |
| 111 | *num = ARRAY_SIZE(early_gpio_table); |
| 112 | return early_gpio_table; |
| 113 | } |
Wisley Chen | a8a7374 | 2019-12-19 18:08:09 +0800 | [diff] [blame] | 114 | |
| 115 | /* |
| 116 | * Default GPIO settings before entering non-S5 sleep states. |
| 117 | * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. |
| 118 | * This guarantees that A12's native3 function is disabled. |
| 119 | * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. |
| 120 | */ |
| 121 | static const struct pad_config default_sleep_gpio_table[] = { |
| 122 | PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ |
| 123 | }; |
| 124 | |
| 125 | /* |
| 126 | * GPIO settings before entering S5, which are same as default_sleep_gpio_table |
| 127 | * but also, turn off FPMCU. |
| 128 | */ |
| 129 | static const struct pad_config s5_sleep_gpio_table[] = { |
| 130 | PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ |
| 131 | PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ |
| 132 | }; |
| 133 | |
| 134 | const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) |
| 135 | { |
| 136 | if (slp_typ == ACPI_S5) { |
| 137 | *num = ARRAY_SIZE(s5_sleep_gpio_table); |
| 138 | return s5_sleep_gpio_table; |
| 139 | } |
| 140 | *num = ARRAY_SIZE(default_sleep_gpio_table); |
| 141 | return default_sleep_gpio_table; |
| 142 | } |
Matt DeVillier | 525c61f | 2022-03-28 23:19:45 -0500 | [diff] [blame^] | 143 | |
| 144 | /* GPIOs needed to be set in romstage. */ |
| 145 | static const struct pad_config romstage_gpio_table[] = { |
| 146 | /* Enable touchscreen, hold in reset */ |
| 147 | /* D9 : EN_PP3300_DX_TOUCHSCREEN */ |
| 148 | PAD_CFG_GPO(GPP_D9, 1, DEEP), |
| 149 | /* D15 : TOUCHSCREEN_RST_L */ |
| 150 | PAD_CFG_GPO(GPP_D15, 0, DEEP), |
| 151 | }; |
| 152 | |
| 153 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 154 | { |
| 155 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 156 | return romstage_gpio_table; |
| 157 | } |