Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <console/console.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <device/device.h> |
| 8 | #include <drivers/intel/pmc_mux/chip.h> |
| 9 | #include <intelblocks/acpi.h> |
| 10 | #include <intelblocks/pmc.h> |
| 11 | #include <intelblocks/pmc_ipc.h> |
| 12 | #include <intelblocks/pmclib.h> |
| 13 | #include <intelblocks/rtc.h> |
| 14 | #include <soc/cpu.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pm.h> |
| 17 | #include <soc/soc_chip.h> |
| 18 | #include <stdint.h> |
| 19 | #include <bootstate.h> |
| 20 | |
| 21 | #define PMC_HID "INTC1026" |
| 22 | |
| 23 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 24 | { |
| 25 | uint32_t reg; |
| 26 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 27 | |
| 28 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 29 | enable ? "En" : "Dis", sx + '0'); |
| 30 | reg = read32(pmcbase + offset); |
| 31 | if (enable) |
| 32 | reg |= mask; |
| 33 | else |
| 34 | reg &= ~mask; |
| 35 | write32(pmcbase + offset, reg); |
| 36 | } |
| 37 | |
| 38 | static void config_deep_s5(int on_ac, int on_dc) |
| 39 | { |
| 40 | /* Treat S4 the same as S5. */ |
| 41 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 42 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 43 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 44 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 45 | } |
| 46 | |
| 47 | static void config_deep_s3(int on_ac, int on_dc) |
| 48 | { |
| 49 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 50 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 51 | } |
| 52 | |
| 53 | static void config_deep_sx(uint32_t deepsx_config) |
| 54 | { |
| 55 | uint32_t reg; |
| 56 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 57 | |
| 58 | reg = read32(pmcbase + DSX_CFG); |
| 59 | reg &= ~DSX_CFG_MASK; |
| 60 | reg |= deepsx_config; |
| 61 | write32(pmcbase + DSX_CFG, reg); |
| 62 | } |
| 63 | |
| 64 | static void soc_pmc_enable(struct device *dev) |
| 65 | { |
| 66 | const config_t *config = config_of_soc(); |
| 67 | |
| 68 | rtc_init(); |
| 69 | |
| 70 | pmc_set_power_failure_state(true); |
| 71 | pmc_gpe_init(); |
| 72 | |
| 73 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 74 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 75 | config_deep_sx(config->deep_sx_config); |
| 76 | } |
| 77 | |
| 78 | static void soc_pmc_read_resources(struct device *dev) |
| 79 | { |
| 80 | struct resource *res; |
| 81 | |
| 82 | /* Add the fixed MMIO resource */ |
Arthur Heymans | 0a60d10 | 2023-07-05 11:59:54 +0200 | [diff] [blame] | 83 | mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 84 | |
| 85 | /* Add the fixed I/O resource */ |
| 86 | res = new_resource(dev, 1); |
| 87 | res->base = (resource_t)ACPI_BASE_ADDRESS; |
| 88 | res->size = (resource_t)ACPI_BASE_SIZE; |
| 89 | res->limit = res->base + res->size - 1; |
| 90 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 91 | } |
| 92 | |
| 93 | static void soc_pmc_fill_ssdt(const struct device *dev) |
| 94 | { |
| 95 | const char *scope = acpi_device_scope(dev); |
| 96 | const char *name = acpi_device_name(dev); |
| 97 | if (!scope || !name) |
| 98 | return; |
| 99 | |
| 100 | acpigen_write_scope(scope); |
| 101 | acpigen_write_device(name); |
| 102 | |
| 103 | acpigen_write_name_string("_HID", PMC_HID); |
| 104 | acpigen_write_name_string("_DDN", "Intel(R) Meteor Lake IPC Controller"); |
Kapil Porwal | c89de22 | 2022-11-14 18:39:21 +0530 | [diff] [blame] | 105 | /* Hide the device so that Windows does not complain on missing driver */ |
| 106 | acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). |
| 110 | * The PMC gets 0xFE000000 - 0xFE00FFFF. |
| 111 | */ |
| 112 | acpigen_write_name("_CRS"); |
| 113 | acpigen_write_resourcetemplate_header(); |
| 114 | acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); |
| 115 | acpigen_write_resourcetemplate_footer(); |
| 116 | |
| 117 | /* Define IPC Write Method */ |
| 118 | if (CONFIG(PMC_IPC_ACPI_INTERFACE)) |
| 119 | pmc_ipc_acpi_fill_ssdt(); |
| 120 | |
| 121 | acpigen_pop_len(); /* PMC Device */ |
| 122 | acpigen_pop_len(); /* Scope */ |
| 123 | |
| 124 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) { |
| 125 | const struct soc_pmc_lpm mtl_pmc_lpm = { |
| 126 | .num_substates = 8, |
| 127 | .num_req_regs = 6, |
| 128 | .lpm_ipc_offset = 0x1000, |
| 129 | .req_reg_stride = 0x30, |
| 130 | .lpm_enable_mask = get_supported_lpm_mask(), |
| 131 | }; |
| 132 | |
| 133 | generate_acpi_power_engine_with_lpm(&mtl_pmc_lpm); |
| 134 | } |
| 135 | |
| 136 | printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, |
| 137 | dev_path(dev)); |
| 138 | } |
| 139 | |
| 140 | static void soc_pmc_init(struct device *dev) |
| 141 | { |
| 142 | /* |
| 143 | * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order |
| 144 | * to ensure the ordering does not break the assumptions that other |
| 145 | * drivers make about ACPI mode (e.g. Chrome EC). Since it disables |
| 146 | * ACPI mode, other drivers may take different actions based on this |
| 147 | * (e.g. Chrome EC will flush any pending hostevent bits). Because |
| 148 | * TGL has its PMC device available for device_operations, it can be |
| 149 | * done from the "ops->init" callback. |
| 150 | */ |
| 151 | pmc_set_acpi_mode(); |
| 152 | |
| 153 | /* |
| 154 | * Disable ACPI PM timer based on Kconfig |
| 155 | * |
| 156 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 157 | * Disabling ACPI PM timer also switches off TCO |
| 158 | */ |
Dinesh Gehlot | 095043f | 2023-08-18 10:04:53 +0530 | [diff] [blame] | 159 | if (!CONFIG(USE_PM_ACPI_TIMER)) |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 160 | setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 164 | { |
| 165 | /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */ |
| 166 | pmc_update_pm1_enable(PWRBTN_EN); |
| 167 | } |
| 168 | |
| 169 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 170 | |
| 171 | /* |
| 172 | * `pmc_final` function is native implementation of equivalent events performed by |
| 173 | * each FSP NotifyPhase() API invocations. |
| 174 | * |
| 175 | * |
| 176 | * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits) |
| 177 | * |
| 178 | * Perform the PMCON status bit clear operation from `.final` |
| 179 | * to cover any such chances where later boot stage requested a global |
| 180 | * reset and PMCON status bit remains set. |
| 181 | */ |
| 182 | static void pmc_final(struct device *dev) |
| 183 | { |
| 184 | pmc_clear_pmcon_sts(); |
| 185 | } |
| 186 | |
| 187 | struct device_operations pmc_ops = { |
| 188 | .read_resources = soc_pmc_read_resources, |
| 189 | .set_resources = noop_set_resources, |
| 190 | .init = soc_pmc_init, |
| 191 | .enable = soc_pmc_enable, |
| 192 | #if CONFIG(HAVE_ACPI_TABLES) |
| 193 | .acpi_fill_ssdt = soc_pmc_fill_ssdt, |
| 194 | #endif |
| 195 | .scan_bus = scan_static_bus, |
| 196 | .final = pmc_final, |
| 197 | }; |