Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <fsp/util.h> |
| 5 | #include <soc/meminit.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 6 | #include <string.h> |
| 7 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 8 | #define LPX_PHYSICAL_CH_WIDTH 16 |
| 9 | #define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) |
| 10 | |
| 11 | #define DDR4_PHYSICAL_CH_WIDTH 64 |
| 12 | #define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH) |
| 13 | |
Meera Ravindranath | be5dc3d | 2021-04-28 15:02:47 +0530 | [diff] [blame] | 14 | #define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 15 | #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) |
| 16 | |
Subrata Banik | efe858b | 2021-03-22 20:08:22 +0530 | [diff] [blame] | 17 | static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) |
| 18 | { |
| 19 | if (mb_cfg->rcomp.resistor != 0) |
| 20 | mem_cfg->RcompResistor = mb_cfg->rcomp.resistor; |
| 21 | |
| 22 | for (size_t i = 0; i < ARRAY_SIZE(mem_cfg->RcompTarget); i++) { |
| 23 | if (mb_cfg->rcomp.targets[i] != 0) |
| 24 | mem_cfg->RcompTarget[i] = mb_cfg->rcomp.targets[i]; |
| 25 | } |
| 26 | } |
| 27 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 28 | static void meminit_lp4x(FSP_M_CONFIG *mem_cfg) |
| 29 | { |
| 30 | mem_cfg->DqPinsInterleaved = 0; |
| 31 | } |
| 32 | |
| 33 | static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config) |
| 34 | { |
| 35 | mem_cfg->DqPinsInterleaved = 0; |
| 36 | mem_cfg->Lp5CccConfig = lp5x_config->ccc_config; |
| 37 | } |
| 38 | |
| 39 | static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) |
| 40 | { |
| 41 | mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved; |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | static const struct soc_mem_cfg soc_mem_cfg[] = { |
| 45 | [MEM_TYPE_DDR4] = { |
| 46 | .num_phys_channels = DDR4_CHANNELS, |
| 47 | .phys_to_mrc_map = { |
| 48 | [0] = 0, |
| 49 | [1] = 4, |
| 50 | }, |
| 51 | .md_phy_masks = { |
| 52 | /* |
| 53 | * Only physical channel 0 is populated in case of half-populated |
| 54 | * configuration. |
| 55 | */ |
| 56 | .half_channel = BIT(0), |
Tim Crawford | 8509c25 | 2022-06-30 10:20:33 -0600 | [diff] [blame] | 57 | /* In mixed topologies, either channel 0 or 1 can be memory-down. */ |
| 58 | .mixed_topo = BIT(0) | BIT(1), |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 59 | }, |
| 60 | }, |
| 61 | [MEM_TYPE_DDR5] = { |
| 62 | .num_phys_channels = DDR5_CHANNELS, |
| 63 | .phys_to_mrc_map = { |
| 64 | [0] = 0, |
Angel Pons | 0e7cf3d | 2022-08-10 20:38:06 +0200 | [diff] [blame] | 65 | [1] = 4, |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 66 | }, |
| 67 | .md_phy_masks = { |
| 68 | /* |
Angel Pons | 0e7cf3d | 2022-08-10 20:38:06 +0200 | [diff] [blame] | 69 | * Only channel 0 is populated in case of half-populated |
| 70 | * configuration. |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 71 | */ |
Angel Pons | 0e7cf3d | 2022-08-10 20:38:06 +0200 | [diff] [blame] | 72 | .half_channel = BIT(0), |
Jeremy Soller | c4731fa | 2023-06-20 14:35:48 -0600 | [diff] [blame] | 73 | /* In mixed topologies, either channel 0 or 1 can be memory-down. */ |
| 74 | .mixed_topo = BIT(0) | BIT(1), |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 75 | }, |
| 76 | }, |
| 77 | [MEM_TYPE_LP4X] = { |
| 78 | .num_phys_channels = LPX_CHANNELS, |
| 79 | .phys_to_mrc_map = { |
| 80 | [0] = 0, |
| 81 | [1] = 1, |
| 82 | [2] = 2, |
| 83 | [3] = 3, |
| 84 | [4] = 4, |
| 85 | [5] = 5, |
| 86 | [6] = 6, |
| 87 | [7] = 7, |
| 88 | }, |
| 89 | .md_phy_masks = { |
| 90 | /* |
| 91 | * Physical channels 0, 1, 2 and 3 are populated in case of |
| 92 | * half-populated configurations. |
| 93 | */ |
| 94 | .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), |
| 95 | /* LP4x does not support mixed topologies. */ |
| 96 | }, |
| 97 | }, |
| 98 | [MEM_TYPE_LP5X] = { |
| 99 | .num_phys_channels = LPX_CHANNELS, |
| 100 | .phys_to_mrc_map = { |
| 101 | [0] = 0, |
| 102 | [1] = 1, |
| 103 | [2] = 2, |
| 104 | [3] = 3, |
| 105 | [4] = 4, |
| 106 | [5] = 5, |
| 107 | [6] = 6, |
| 108 | [7] = 7, |
| 109 | }, |
| 110 | .md_phy_masks = { |
| 111 | /* |
| 112 | * Physical channels 0, 1, 2 and 3 are populated in case of |
| 113 | * half-populated configurations. |
| 114 | */ |
| 115 | .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), |
| 116 | /* LP5x does not support mixed topologies. */ |
| 117 | }, |
| 118 | }, |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 119 | }; |
| 120 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 121 | static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 122 | { |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 123 | uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 124 | [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, |
| 125 | [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, |
| 126 | [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, }, |
| 127 | [3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, }, |
| 128 | [4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, }, |
| 129 | [5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, }, |
| 130 | [6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, }, |
| 131 | [7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, }, |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 132 | }; |
Bora Guvendik | 64b1352 | 2021-05-10 14:59:25 -0700 | [diff] [blame] | 133 | uint8_t *disable_channel_upds[MRC_CHANNELS] = { |
Ronak Kanabar | c4813ea | 2021-05-12 18:44:30 +0530 | [diff] [blame] | 134 | &mem_cfg->DisableMc0Ch0, |
| 135 | &mem_cfg->DisableMc0Ch1, |
| 136 | &mem_cfg->DisableMc0Ch2, |
| 137 | &mem_cfg->DisableMc0Ch3, |
| 138 | &mem_cfg->DisableMc1Ch0, |
| 139 | &mem_cfg->DisableMc1Ch1, |
| 140 | &mem_cfg->DisableMc1Ch2, |
| 141 | &mem_cfg->DisableMc1Ch3, |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 142 | }; |
| 143 | size_t ch, dimm; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 144 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 145 | mem_cfg->MemorySpdDataLen = data->spd_len; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 146 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 147 | for (ch = 0; ch < MRC_CHANNELS; ch++) { |
Bora Guvendik | 64b1352 | 2021-05-10 14:59:25 -0700 | [diff] [blame] | 148 | uint8_t *disable_channel_ptr = disable_channel_upds[ch]; |
| 149 | bool enable_channel = 0; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 150 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 151 | for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { |
| 152 | uint32_t *spd_ptr = spd_upds[ch][dimm]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 153 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 154 | *spd_ptr = data->spd[ch][dimm]; |
Bora Guvendik | 64b1352 | 2021-05-10 14:59:25 -0700 | [diff] [blame] | 155 | if (*spd_ptr) |
| 156 | enable_channel = 1; |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 157 | } |
Bora Guvendik | 64b1352 | 2021-05-10 14:59:25 -0700 | [diff] [blame] | 158 | *disable_channel_ptr = !enable_channel; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 159 | } |
| 160 | } |
| 161 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 162 | static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, |
| 163 | const struct mem_channel_data *data, bool auto_detect) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 164 | { |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 165 | size_t i; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 166 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 167 | for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) { |
| 168 | if (auto_detect || |
| 169 | !channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags)) |
| 170 | memset(upds[i], 0, upd_size); |
| 171 | else |
| 172 | memcpy(upds[i], map, upd_size); |
| 173 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 174 | } |
| 175 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 176 | static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, |
| 177 | const struct mb_cfg *mb_cfg, bool auto_detect) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 178 | { |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 179 | void *dq_upds[MRC_CHANNELS] = { |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 180 | &mem_cfg->DqMapCpu2DramMc0Ch0, |
| 181 | &mem_cfg->DqMapCpu2DramMc0Ch1, |
| 182 | &mem_cfg->DqMapCpu2DramMc0Ch2, |
| 183 | &mem_cfg->DqMapCpu2DramMc0Ch3, |
| 184 | &mem_cfg->DqMapCpu2DramMc1Ch0, |
| 185 | &mem_cfg->DqMapCpu2DramMc1Ch1, |
| 186 | &mem_cfg->DqMapCpu2DramMc1Ch2, |
| 187 | &mem_cfg->DqMapCpu2DramMc1Ch3, |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 188 | }; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 189 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 190 | const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 191 | |
Arthur Heymans | b438959 | 2022-02-18 13:24:07 +0100 | [diff] [blame] | 192 | _Static_assert(sizeof(mem_cfg->DqMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH, |
| 193 | "Incorrect DQ UPD size!"); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 194 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 195 | mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 196 | } |
| 197 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 198 | static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, |
| 199 | const struct mb_cfg *mb_cfg, bool auto_detect) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 200 | { |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 201 | void *dqs_upds[MRC_CHANNELS] = { |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 202 | &mem_cfg->DqsMapCpu2DramMc0Ch0, |
| 203 | &mem_cfg->DqsMapCpu2DramMc0Ch1, |
| 204 | &mem_cfg->DqsMapCpu2DramMc0Ch2, |
| 205 | &mem_cfg->DqsMapCpu2DramMc0Ch3, |
| 206 | &mem_cfg->DqsMapCpu2DramMc1Ch0, |
| 207 | &mem_cfg->DqsMapCpu2DramMc1Ch1, |
| 208 | &mem_cfg->DqsMapCpu2DramMc1Ch2, |
| 209 | &mem_cfg->DqsMapCpu2DramMc1Ch3, |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 210 | }; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 211 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 212 | const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 213 | |
Arthur Heymans | b438959 | 2022-02-18 13:24:07 +0100 | [diff] [blame] | 214 | _Static_assert(sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH / 8, |
| 215 | "Incorrect DQS UPD size!"); |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 216 | |
| 217 | mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); |
| 218 | } |
| 219 | |
Meera Ravindranath | 91a1276 | 2021-02-22 09:53:43 +0530 | [diff] [blame] | 220 | #define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) |
| 221 | |
| 222 | static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, |
| 223 | const struct mem_spd *spd_info) |
| 224 | { |
| 225 | for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { |
| 226 | for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { |
| 227 | size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; |
| 228 | mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = |
| 229 | spd_info->smbus[ch].addr_dimm[dimm] << 1; |
| 230 | } |
| 231 | } |
| 232 | mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); |
| 233 | mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); |
| 234 | } |
| 235 | |
Subrata Banik | 2eb51aa | 2022-03-10 17:53:14 +0530 | [diff] [blame] | 236 | void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, |
Subrata Banik | 4703edc | 2022-03-10 19:12:02 +0530 | [diff] [blame] | 237 | const struct mem_spd *spd_info, bool half_populated) |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 238 | { |
| 239 | struct mem_channel_data data; |
| 240 | bool dq_dqs_auto_detect = false; |
Subrata Banik | 2eb51aa | 2022-03-10 17:53:14 +0530 | [diff] [blame] | 241 | FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 242 | |
Michał Żygowski | 9ec479d | 2023-08-03 12:50:01 +0200 | [diff] [blame] | 243 | #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) |
Kane Chen | caa8a20 | 2023-05-08 14:25:10 +0800 | [diff] [blame] | 244 | mem_cfg->CsPiStartHighinEct = mb_cfg->cs_pi_start_high_in_ect; |
| 245 | #endif |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 246 | mem_cfg->ECT = mb_cfg->ect; |
| 247 | mem_cfg->UserBd = mb_cfg->UserBd; |
Subrata Banik | efe858b | 2021-03-22 20:08:22 +0530 | [diff] [blame] | 248 | set_rcomp_config(mem_cfg, mb_cfg); |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 249 | |
Maulik V Vaghela | 91b2024 | 2021-02-23 14:03:43 +0530 | [diff] [blame] | 250 | /* Fill command mirror for memory */ |
| 251 | mem_cfg->CmdMirror = mb_cfg->CmdMirror; |
| 252 | |
| 253 | /* Fill LpDdrrDqDqs Retraining for memory */ |
| 254 | mem_cfg->LpDdrDqDqsReTraining = mb_cfg->LpDdrDqDqsReTraining; |
| 255 | |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 256 | switch (mb_cfg->type) { |
| 257 | case MEM_TYPE_DDR4: |
Meera Ravindranath | 91a1276 | 2021-02-22 09:53:43 +0530 | [diff] [blame] | 258 | meminit_ddr(mem_cfg, &mb_cfg->ddr_config); |
| 259 | dq_dqs_auto_detect = true; |
| 260 | break; |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 261 | case MEM_TYPE_DDR5: |
| 262 | meminit_ddr(mem_cfg, &mb_cfg->ddr_config); |
| 263 | dq_dqs_auto_detect = true; |
Meera Ravindranath | 91a1276 | 2021-02-22 09:53:43 +0530 | [diff] [blame] | 264 | /* |
| 265 | * TODO: Drop this workaround once SMBus driver in coreboot is updated to |
| 266 | * support DDR5 EEPROM reading. |
| 267 | */ |
| 268 | if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { |
| 269 | ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); |
| 270 | return; |
| 271 | } |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 272 | break; |
| 273 | case MEM_TYPE_LP4X: |
| 274 | meminit_lp4x(mem_cfg); |
| 275 | break; |
| 276 | case MEM_TYPE_LP5X: |
| 277 | meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); |
| 278 | break; |
| 279 | default: |
| 280 | die("Unsupported memory type(%d)\n", mb_cfg->type); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 281 | } |
| 282 | |
Subrata Banik | 47b836a | 2022-03-10 17:21:33 +0530 | [diff] [blame] | 283 | mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, |
Subrata Banik | 4703edc | 2022-03-10 19:12:02 +0530 | [diff] [blame] | 284 | &data); |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 285 | mem_init_spd_upds(mem_cfg, &data); |
| 286 | mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); |
| 287 | mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 288 | } |