Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Aaron Durbin | 8cbf47f | 2013-12-04 11:03:20 -0600 | [diff] [blame] | 20 | #include <arch/io.h> |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | |
Aaron Durbin | 8cbf47f | 2013-12-04 11:03:20 -0600 | [diff] [blame] | 26 | #include <baytrail/iomap.h> |
| 27 | #include <baytrail/pci_devs.h> |
| 28 | #include <baytrail/pmc.h> |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 29 | #include <baytrail/ramstage.h> |
Aaron Durbin | 8cbf47f | 2013-12-04 11:03:20 -0600 | [diff] [blame] | 30 | #include "chip.h" |
| 31 | |
| 32 | |
Aaron Durbin | f4fe3c3 | 2013-12-09 12:52:37 -0600 | [diff] [blame] | 33 | /* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB |
| 34 | * address. Just take 1MiB @ 512MiB. */ |
| 35 | #define FIRMWARE_PHYS_BASE (512 << 20) |
| 36 | #define FIRMWARE_PHYS_LENGTH (1 << 20) |
| 37 | #define FIRMWARE_REG_BASE 0xa8 |
| 38 | #define FIRMWARE_REG_LENGTH 0xac |
| 39 | |
Aaron Durbin | 8cbf47f | 2013-12-04 11:03:20 -0600 | [diff] [blame] | 40 | static void setup_codec_clock(device_t dev) |
| 41 | { |
| 42 | uint32_t reg; |
| 43 | int clk_reg; |
| 44 | struct soc_intel_baytrail_config *config; |
| 45 | const char *freq_str; |
| 46 | |
| 47 | config = dev->chip_info; |
| 48 | switch (config->lpe_codec_clk_freq) { |
| 49 | case 19: |
| 50 | freq_str = "19.2"; |
| 51 | reg = CLK_FREQ_19P2MHZ; |
| 52 | break; |
| 53 | case 25: |
| 54 | freq_str = "25"; |
| 55 | reg = CLK_FREQ_25MHZ; |
| 56 | break; |
| 57 | default: |
| 58 | printk(BIOS_DEBUG, "LPE codec clock not required.\n"); |
| 59 | return; |
| 60 | } |
| 61 | |
| 62 | /* Default to always running. */ |
| 63 | reg |= CLK_CTL_ON; |
| 64 | |
| 65 | if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { |
| 66 | printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); |
| 67 | return; |
| 68 | } |
| 69 | |
| 70 | printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); |
| 71 | |
| 72 | clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0; |
| 73 | clk_reg += 4 * config->lpe_codec_clk_num; |
| 74 | |
| 75 | write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); |
| 76 | } |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 77 | |
| 78 | static void lpe_init(device_t dev) |
| 79 | { |
Aaron Durbin | 8cbf47f | 2013-12-04 11:03:20 -0600 | [diff] [blame] | 80 | setup_codec_clock(dev); |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 81 | } |
| 82 | |
Aaron Durbin | f4fe3c3 | 2013-12-09 12:52:37 -0600 | [diff] [blame] | 83 | static void lpe_read_resources(device_t dev) |
| 84 | { |
| 85 | pci_dev_read_resources(dev); |
| 86 | |
| 87 | reserved_ram_resource(dev, FIRMWARE_REG_BASE, |
| 88 | FIRMWARE_PHYS_BASE >> 10, |
| 89 | FIRMWARE_PHYS_LENGTH >> 10); |
| 90 | } |
| 91 | |
| 92 | static void lpe_set_resources(device_t dev) |
| 93 | { |
| 94 | struct resource *res; |
| 95 | |
| 96 | pci_dev_set_resources(dev); |
| 97 | |
| 98 | res = find_resource(dev, FIRMWARE_REG_BASE); |
| 99 | if (res == NULL) { |
| 100 | printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); |
| 101 | return; |
| 102 | } |
| 103 | pci_write_config32(dev, FIRMWARE_REG_BASE, res->base); |
| 104 | pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size); |
| 105 | } |
| 106 | |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 107 | static const struct device_operations device_ops = { |
Aaron Durbin | f4fe3c3 | 2013-12-09 12:52:37 -0600 | [diff] [blame] | 108 | .read_resources = lpe_read_resources, |
| 109 | .set_resources = lpe_set_resources, |
Aaron Durbin | 4334c87 | 2013-12-05 11:12:15 -0600 | [diff] [blame] | 110 | .enable_resources = pci_dev_enable_resources, |
Aaron Durbin | 97651c5 | 2013-11-01 14:36:03 -0500 | [diff] [blame] | 111 | .init = lpe_init, |
| 112 | .enable = NULL, |
| 113 | .scan_bus = NULL, |
| 114 | .ops_pci = &soc_pci_ops, |
| 115 | }; |
| 116 | |
| 117 | static const struct pci_driver southcluster __pci_driver = { |
| 118 | .ops = &device_ops, |
| 119 | .vendor = PCI_VENDOR_ID_INTEL, |
| 120 | .device = LPE_DEVID, |
| 121 | }; |