blob: 41be89ace12fa12ca1804a71199a7066008ed7d9 [file] [log] [blame]
Aamir Bohradd7acaa2020-03-25 11:36:22 +05301/*
2 * This file is part of the coreboot project.
3 *
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
Aamir Bohra512b77a2020-03-25 13:20:34 +053015#include <soc/gpe.h>
16
17/* XHCI Controller 0:14.0 */
18
19Device (XHCI)
20{
21 Name (_ADR, 0x00140000)
22
23 Name (_PRW, Package () { GPE0_PME_B0, 3 })
24
25 Name (_S3D, 3) /* D3 supported in S3 */
26 Name (_S0W, 3) /* D3 can wake device in S0 */
27 Name (_S3W, 3) /* D3 can wake system from S3 */
28
29 Method (_PS0, 0, Serialized)
30 {
31
32 }
33
34 Method (_PS3, 0, Serialized)
35 {
36
37 }
38
39 /* Root Hub for Jasperlake PCH */
40 Device (RHUB)
41 {
42 Name (_ADR, Zero)
43
44 /* USB2 */
45 Device (HS01) { Name (_ADR, 1) }
46 Device (HS02) { Name (_ADR, 2) }
47 Device (HS03) { Name (_ADR, 3) }
48 Device (HS04) { Name (_ADR, 4) }
49 Device (HS05) { Name (_ADR, 5) }
50 Device (HS06) { Name (_ADR, 6) }
51 Device (HS07) { Name (_ADR, 7) }
52 Device (HS08) { Name (_ADR, 8) }
53
54 /* USB3 */
55 Device (SS01) { Name (_ADR, 9) }
56 Device (SS02) { Name (_ADR, 10) }
57 Device (SS03) { Name (_ADR, 11) }
58 Device (SS04) { Name (_ADR, 12) }
59 Device (SS05) { Name (_ADR, 13) }
60 Device (SS06) { Name (_ADR, 14) }
61 }
62}