Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi_ivrs.h> |
| 4 | #include <amdblocks/acpi.h> |
| 5 | #include <amdblocks/cpu.h> |
| 6 | #include <amdblocks/data_fabric.h> |
| 7 | #include <amdblocks/ioapic.h> |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <cpu/amd/cpuid.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 11 | #include <device/device.h> |
Elyes Haouas | 8823ba1 | 2022-12-05 08:48:50 +0100 | [diff] [blame] | 12 | #include <device/mmio.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 13 | #include <device/pci_def.h> |
| 14 | #include <device/pci_ops.h> |
| 15 | #include <soc/acpi.h> |
| 16 | #include <soc/data_fabric.h> |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 17 | #include <soc/iomap.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 18 | #include <soc/pci_devs.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 19 | |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 20 | static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 21 | uint16_t src_devid, uint8_t dte_setting) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 22 | { |
| 23 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 24 | memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); |
| 25 | |
| 26 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 27 | ivhd_ioapic->dte_setting = dte_setting; |
| 28 | ivhd_ioapic->handle = get_ioapic_id(ioapic_base); |
| 29 | ivhd_ioapic->source_dev_id = src_devid; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 30 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 31 | current += sizeof(ivrs_ivhd_special_t); |
| 32 | |
| 33 | return current; |
| 34 | } |
| 35 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 36 | static unsigned long ivhd_describe_hpet(unsigned long current, uint8_t hndl, uint16_t src_devid) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 37 | { |
| 38 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
Felix Held | 56167c5 | 2023-06-22 23:22:19 +0200 | [diff] [blame] | 39 | memset(ivhd_hpet, 0, sizeof(*ivhd_hpet)); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 40 | |
| 41 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 42 | ivhd_hpet->handle = hndl; |
| 43 | ivhd_hpet->source_dev_id = src_devid; /* function 0 of FCH PCI device */ |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 44 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 45 | current += sizeof(ivrs_ivhd_special_t); |
| 46 | |
| 47 | return current; |
| 48 | } |
| 49 | |
Felix Held | 534cce3 | 2023-06-22 23:09:23 +0200 | [diff] [blame] | 50 | static unsigned long ivhd_describe_f0_device(unsigned long current, uint16_t dev_id, |
| 51 | const char acpi_hid[8], uint8_t datasetting) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 52 | { |
Elyes Haouas | 68fc51f | 2022-07-16 09:48:27 +0200 | [diff] [blame] | 53 | ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *)current; |
Felix Held | 63a4e6bd | 2023-06-22 23:04:19 +0200 | [diff] [blame] | 54 | memset(ivhd_f0, 0, sizeof(*ivhd_f0)); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 55 | |
| 56 | ivhd_f0->type = IVHD_DEV_VARIABLE; |
| 57 | ivhd_f0->dev_id = dev_id; |
| 58 | ivhd_f0->dte_setting = datasetting; |
Felix Held | 534cce3 | 2023-06-22 23:09:23 +0200 | [diff] [blame] | 59 | |
| 60 | memcpy(ivhd_f0->hardware_id, acpi_hid, sizeof(ivhd_f0->hardware_id)); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 61 | |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 62 | current += sizeof(ivrs_ivhd_f0_entry_t); |
| 63 | return current; |
| 64 | } |
| 65 | |
| 66 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 67 | uint16_t end_devid, uint8_t setting) |
| 68 | { |
| 69 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 70 | current = ALIGN_UP(current, 4); |
| 71 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 72 | |
| 73 | /* Create the start range IVHD entry */ |
| 74 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 75 | ivhd_range->dev_id = start_devid; |
| 76 | ivhd_range->dte_setting = setting; |
| 77 | current += sizeof(ivrs_ivhd_generic_t); |
| 78 | |
| 79 | /* Create the end range IVHD entry */ |
| 80 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 81 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 82 | ivhd_range->dev_id = end_devid; |
| 83 | ivhd_range->dte_setting = setting; |
| 84 | current += sizeof(ivrs_ivhd_generic_t); |
| 85 | |
| 86 | return current; |
| 87 | } |
| 88 | |
| 89 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 90 | unsigned long *current, uint8_t type, uint8_t data) |
| 91 | { |
| 92 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 93 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 94 | *current = ALIGN_UP(*current, 4); |
| 95 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 96 | |
| 97 | ivhd_entry->type = type; |
| 98 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 99 | ivhd_entry->dte_setting = data; |
| 100 | *current += sizeof(ivrs_ivhd_generic_t); |
| 101 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 102 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 103 | |
| 104 | ivhd_entry->type = type; |
| 105 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 106 | ivhd_entry->dte_setting = data; |
| 107 | ivhd_entry->reserved1 = 0; |
| 108 | ivhd_entry->reserved2 = 0; |
| 109 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 110 | (parent->bus->secondary << 8); |
| 111 | *current += sizeof(ivrs_ivhd_alias_t); |
| 112 | } |
| 113 | |
| 114 | return *current; |
| 115 | } |
| 116 | |
| 117 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 118 | unsigned long *current) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 119 | { |
| 120 | unsigned int header_type, is_pcie; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 121 | |
| 122 | header_type = dev->hdr_type & 0x7f; |
| 123 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 124 | |
| 125 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 126 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 127 | /* Device or Bridge is PCIe */ |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 128 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 129 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 130 | /* Device is legacy PCI or PCI-X */ |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 131 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 132 | |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 133 | } |
| 134 | } |
| 135 | |
| 136 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
| 137 | unsigned int depth, int linknum, int8_t *root_level, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 138 | unsigned long *current, uint16_t nb_bus) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 139 | { |
| 140 | struct device *sibling; |
| 141 | struct bus *link; |
| 142 | |
| 143 | if (!root_level) |
| 144 | return; |
| 145 | |
| 146 | if (dev->path.type == DEVICE_PATH_PCI) { |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 147 | if ((dev->bus->secondary == nb_bus) && |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 148 | (dev->path.pci.devfn == 0x0)) |
| 149 | *root_level = depth; |
| 150 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 151 | if ((*root_level != -1) && (dev->enabled)) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 152 | if (depth != *root_level) |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 153 | ivrs_add_device_or_bridge(parent, dev, current); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | for (link = dev->link_list; link; link = link->next) |
| 157 | for (sibling = link->children; sibling; sibling = |
| 158 | sibling->sibling) |
| 159 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 160 | current, nb_bus); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 163 | static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev) |
| 164 | { |
| 165 | u8 dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 166 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 167 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
| 168 | int8_t root_level = -1; |
| 169 | struct resource *res; |
| 170 | |
| 171 | /* |
| 172 | * Add all possible PCI devices in the domain that can generate transactions |
| 173 | * processed by IOMMU. Start with device <bus>:01.0 |
| 174 | */ |
| 175 | current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->link_list->secondary << 8), |
| 176 | 0xff | (dev->link_list->subordinate << 8), 0); |
| 177 | |
| 178 | add_ivhd_device_entries(NULL, dev, 0, -1, &root_level, |
| 179 | ¤t, dev->link_list->secondary); |
| 180 | |
| 181 | res = probe_resource(dev, IOMMU_IOAPIC_IDX); |
| 182 | if (res) { |
| 183 | /* Describe IOAPIC associated with the IOMMU */ |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 184 | current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 185 | PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | /* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */ |
| 189 | if (dev->link_list->secondary == 0) { |
| 190 | /* Describe HPET */ |
| 191 | current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); |
| 192 | /* Describe FCH IOAPICs */ |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 193 | current = acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 194 | SMBUS_DEVFN, dte_setting); |
| 195 | } |
| 196 | |
| 197 | return current; |
| 198 | } |
| 199 | |
| 200 | static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *ivhd, |
| 201 | struct device *nb_dev, struct device *iommu_dev) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 202 | { |
| 203 | acpi_ivrs_ivhd40_t *ivhd_40; |
| 204 | unsigned long current_backup; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 205 | |
| 206 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); |
| 207 | ivhd_40 = (acpi_ivrs_ivhd40_t *)current; |
| 208 | |
| 209 | /* Enable EFR */ |
| 210 | ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; |
| 211 | /* For type 40h bits 6 and 7 are reserved */ |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 212 | ivhd_40->flags = ivhd->flags & 0x3f; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 213 | ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); |
| 214 | /* BDF <bus>:00.2 */ |
| 215 | ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 216 | ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 217 | ivhd_40->iommu_base_low = ivhd->iommu_base_low; |
| 218 | ivhd_40->iommu_base_high = ivhd->iommu_base_high; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 219 | ivhd_40->pci_segment_group = 0x0000; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 220 | ivhd_40->iommu_info = ivhd->iommu_info; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 221 | /* For type 40h bits 31:28 and 12:0 are reserved */ |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 222 | ivhd_40->iommu_attributes = ivhd->iommu_feature_info & 0xfffe000; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 223 | |
| 224 | if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { |
Arthur Heymans | 4c68487 | 2022-04-19 21:44:22 +0200 | [diff] [blame] | 225 | ivhd_40->efr_reg_image_low = read32p(ivhd_40->iommu_base_low + 0x30); |
| 226 | ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | current += sizeof(acpi_ivrs_ivhd40_t); |
| 230 | |
| 231 | /* Now repeat all the device entries from type 10h */ |
| 232 | current_backup = current; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 233 | current = acpi_ivhd_misc(current, nb_dev->bus->dev); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 234 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 235 | if (nb_dev->bus->secondary == 0) { |
| 236 | /* Describe EMMC */ |
Felix Held | 47ed271 | 2023-06-20 19:17:43 +0200 | [diff] [blame] | 237 | if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) { |
| 238 | /* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the |
| 239 | * reference code uses. Maybe to have a unique PCI device to put into |
| 240 | * the field that doesn't collide with any existing device? */ |
| 241 | current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), |
Felix Held | 534cce3 | 2023-06-22 23:09:23 +0200 | [diff] [blame] | 242 | "AMDI0040", |
Felix Held | 47ed271 | 2023-06-20 19:17:43 +0200 | [diff] [blame] | 243 | IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 244 | IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | |
| 245 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); |
| 246 | } |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 247 | } |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 248 | ivhd_40->length += (current - current_backup); |
| 249 | |
| 250 | return current; |
| 251 | } |
| 252 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 253 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *ivhd, |
| 254 | struct device *nb_dev, struct device *iommu_dev) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 255 | { |
| 256 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 257 | ivhd11_iommu_attr_t *ivhd11_attr_ptr; |
| 258 | unsigned long current_backup; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 259 | |
| 260 | /* |
| 261 | * In order to utilize all features, firmware should expose type 11h |
| 262 | * IVHD which supersedes the type 10h. |
| 263 | */ |
| 264 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 265 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
| 266 | |
| 267 | /* Enable EFR */ |
| 268 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 269 | /* For type 11h bits 6 and 7 are reserved */ |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 270 | ivhd_11->flags = ivhd->flags & 0x3f; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 271 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 272 | /* BDF <bus>:00.2 */ |
| 273 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 274 | ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 275 | ivhd_11->iommu_base_low = ivhd->iommu_base_low; |
| 276 | ivhd_11->iommu_base_high = ivhd->iommu_base_high; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 277 | ivhd_11->pci_segment_group = 0x0000; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 278 | ivhd_11->iommu_info = ivhd->iommu_info; |
| 279 | ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivhd->iommu_feature_info; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 280 | ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; |
| 281 | ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks; |
| 282 | ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; |
| 283 | |
| 284 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { |
Arthur Heymans | 4c68487 | 2022-04-19 21:44:22 +0200 | [diff] [blame] | 285 | ivhd_11->efr_reg_image_low = read32p(ivhd_11->iommu_base_low + 0x30); |
| 286 | ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 290 | |
| 291 | /* Now repeat all the device entries from type 10h */ |
| 292 | current_backup = current; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 293 | current = acpi_ivhd_misc(current, nb_dev->bus->dev); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 294 | ivhd_11->length += (current - current_backup); |
| 295 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 296 | return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 300 | { |
| 301 | unsigned long current_backup; |
| 302 | uint64_t mmio_x30_value; |
| 303 | uint64_t mmio_x18_value; |
| 304 | uint64_t mmio_x4000_value; |
| 305 | uint32_t cap_offset_0; |
| 306 | uint32_t cap_offset_10; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 307 | struct acpi_ivrs_ivhd *ivhd; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 308 | struct device *iommu_dev; |
| 309 | struct device *nb_dev; |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 310 | struct device *dev = NULL; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 311 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 312 | ivhd = &ivrs->ivhd; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 313 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 314 | while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 315 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 316 | nb_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); |
| 317 | iommu_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 2)); |
| 318 | if (!nb_dev) { |
| 319 | printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); |
| 320 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 321 | return (unsigned long)ivrs; |
| 322 | } |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 323 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 324 | if (!iommu_dev) { |
| 325 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 326 | return (unsigned long)ivrs; |
| 327 | } |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 328 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 329 | ivhd->type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 330 | ivhd->length = sizeof(struct acpi_ivrs_ivhd); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 331 | |
| 332 | /* BDF <bus>:00.2 */ |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 333 | ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 334 | ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
| 335 | ivhd->iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; |
| 336 | ivhd->iommu_base_high = pci_read_config32(iommu_dev, 0x48); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 337 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 338 | cap_offset_0 = pci_read_config32(iommu_dev, ivhd->capability_offset); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 339 | cap_offset_10 = pci_read_config32(iommu_dev, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 340 | ivhd->capability_offset + 0x10); |
| 341 | mmio_x18_value = read64p(ivhd->iommu_base_low + 0x18); |
| 342 | mmio_x30_value = read64p(ivhd->iommu_base_low + 0x30); |
| 343 | mmio_x4000_value = read64p(ivhd->iommu_base_low + 0x4000); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 344 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 345 | ivhd->flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 346 | IVHD_FLAG_PPE_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 347 | ivhd->flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PRE_F_SUP) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 348 | IVHD_FLAG_PREF_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 349 | ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_COHERENT) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 350 | IVHD_FLAG_COHERENT : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 351 | ivhd->flags |= ((cap_offset_0 & CAP_OFFSET_0_IOTLB_SP) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 352 | IVHD_FLAG_IOTLB_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 353 | ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_ISOC) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 354 | IVHD_FLAG_ISOC : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 355 | ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_RES_PASS_PW) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 356 | IVHD_FLAG_RES_PASS_PW : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 357 | ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_PASS_PW) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 358 | IVHD_FLAG_PASS_PW : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 359 | ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 360 | IVHD_FLAG_HT_TUN_EN : 0); |
| 361 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 362 | ivhd->pci_segment_group = 0x0000; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 363 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 364 | ivhd->iommu_info = pci_read_config16(iommu_dev, |
| 365 | ivhd->capability_offset + 0x10) & 0x1F; |
| 366 | ivhd->iommu_info |= (pci_read_config16(iommu_dev, |
| 367 | ivhd->capability_offset + 0xC) & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 368 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 369 | ivhd->iommu_feature_info = 0; |
| 370 | ivhd->iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_HATS_MASK) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 371 | << (IOMMU_FEATURE_HATS_SHIFT - MMIO_EXT_FEATURE_HATS_SHIFT); |
| 372 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 373 | ivhd->iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_GATS_MASK) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 374 | << (IOMMU_FEATURE_GATS_SHIFT - MMIO_EXT_FEATURE_GATS_SHIFT); |
| 375 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 376 | ivhd->iommu_feature_info |= (cap_offset_10 & CAP_OFFSET_10_MSI_NUM_PPR) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 377 | >> (CAP_OFFSET_10_MSI_NUM_PPR_SHIFT |
| 378 | - IOMMU_FEATURE_MSI_NUM_PPR_SHIFT); |
| 379 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 380 | ivhd->iommu_feature_info |= (mmio_x4000_value & |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 381 | MMIO_CNT_CFG_N_COUNTER_BANKS) |
| 382 | << (IOMMU_FEATURE_PN_BANKS_SHIFT - MMIO_CNT_CFG_N_CNT_BANKS_SHIFT); |
| 383 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 384 | ivhd->iommu_feature_info |= (mmio_x4000_value & MMIO_CNT_CFG_N_COUNTER) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 385 | << (IOMMU_FEATURE_PN_COUNTERS_SHIFT - MMIO_CNT_CFG_N_COUNTER_SHIFT); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 386 | ivhd->iommu_feature_info |= (mmio_x30_value & |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 387 | MMIO_EXT_FEATURE_PAS_MAX_MASK) |
| 388 | >> (MMIO_EXT_FEATURE_PAS_MAX_SHIFT - IOMMU_FEATURE_PA_SMAX_SHIFT); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 389 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_HE_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 390 | ? IOMMU_FEATURE_HE_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 391 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GA_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 392 | ? IOMMU_FEATURE_GA_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 393 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_IA_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 394 | ? IOMMU_FEATURE_IA_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 395 | ivhd->iommu_feature_info |= (mmio_x30_value & |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 396 | MMIO_EXT_FEATURE_GLX_SUP_MASK) |
| 397 | >> (MMIO_EXT_FEATURE_GLX_SHIFT - IOMMU_FEATURE_GLX_SHIFT); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 398 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GT_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 399 | ? IOMMU_FEATURE_GT_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 400 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_NX_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 401 | ? IOMMU_FEATURE_NX_SUP : 0); |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 402 | ivhd->iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_XT_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 403 | ? IOMMU_FEATURE_XT_SUP : 0); |
| 404 | |
| 405 | /* Enable EFR if supported */ |
| 406 | ivrs->iv_info = pci_read_config32(iommu_dev, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 407 | ivhd->capability_offset + 0x10) & 0x007fffe0; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 408 | if (pci_read_config32(iommu_dev, |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 409 | ivhd->capability_offset) & EFR_FEATURE_SUP) |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 410 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
| 411 | |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 412 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 413 | current_backup = current; |
| 414 | current = acpi_ivhd_misc(current, dev); |
| 415 | ivhd->length += (current - current_backup); |
| 416 | |
| 417 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 418 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 419 | return current; |
| 420 | |
| 421 | current = acpi_fill_ivrs11(current, ivhd, nb_dev, iommu_dev); |
| 422 | |
| 423 | ivhd = (struct acpi_ivrs_ivhd *)current; |
| 424 | current += sizeof(struct acpi_ivrs_ivhd); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 425 | } |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 426 | current -= sizeof(struct acpi_ivrs_ivhd); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 427 | |
Naresh Solanki | 4ef89f7 | 2023-05-25 17:37:50 +0200 | [diff] [blame] | 428 | return current; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 429 | } |