Angel Pons | 585495e | 2020-04-03 01:21:38 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | b28f466 | 2018-05-26 17:58:47 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 3 | #include <device/pci_ops.h> |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Angel Pons | 22a6d11 | 2020-06-21 18:50:22 +0200 | [diff] [blame] | 5 | #include <southbridge/intel/common/early_spi.h> |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/i82801ix/i82801ix.h> |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 7 | |
Angel Pons | 899525d | 2021-01-28 10:57:13 +0100 | [diff] [blame] | 8 | #include "q35.h" |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 9 | |
| 10 | static void bootblock_northbridge_init(void) |
| 11 | { |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 12 | /* |
| 13 | * The "io" variant of the config access is explicitly used to |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 14 | * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 15 | * to true. That way all subsequent non-explicit config accesses use |
| 16 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 17 | * the first thing called in the non-asm boot block code. The final |
| 18 | * assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 19 | * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 20 | * |
| 21 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 22 | * 4GiB. |
| 23 | */ |
Angel Pons | cba669c | 2021-01-28 11:56:45 +0100 | [diff] [blame] | 24 | const uint32_t pciexbar = make_pciexbar(); |
| 25 | pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0); |
| 26 | pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar); |
Patrick Rudolph | fbdeb4a | 2019-02-14 19:47:03 +0100 | [diff] [blame] | 27 | |
Angel Pons | cba669c | 2021-01-28 11:56:45 +0100 | [diff] [blame] | 28 | if (CONFIG(BOOTBLOCK_CONSOLE)) |
| 29 | mainboard_machine_check(); |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 30 | } |
| 31 | |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 32 | static void bootblock_southbridge_init(void) |
| 33 | { |
Angel Pons | 22a6d11 | 2020-06-21 18:50:22 +0200 | [diff] [blame] | 34 | enable_spi_prefetching_and_caching(); |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 35 | |
| 36 | /* Enable RCBA */ |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 37 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 38 | CONFIG_FIXED_RCBA_MMIO_BASE | 1); |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | void bootblock_soc_init(void) |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 42 | { |
| 43 | bootblock_northbridge_init(); |
| 44 | bootblock_southbridge_init(); |
| 45 | } |