blob: 205fd2bc3bec73720a5a51c576185ee5ebbae8f2 [file] [log] [blame]
Robert Chenff153962023-08-18 04:38:03 -04001fw_config
2 field DB_USB 0 1
3 option DB_NONE 0
4 option DB_1C_1A 1
Robert Chen50829632023-11-28 02:24:58 -05005 option DB_LTE 2
Robert Chenff153962023-08-18 04:38:03 -04006 option DB_1C_LTE 3
7 end
8 field WIFI_SAR_ID 2 3
9 option SAR_ID_0 0
10 option SAR_ID_1 1
11 option SAR_ID_2 2
12 option SAR_ID_3 3
13 end
14 field STYLUS 9
15 option STYLUS_ABSENT 0
16 option STYLUS_PRESENT 1
17 end
18 field SD_CARD 10
19 option SD_PRESENT 0
20 option SD_ABSENT 1
21 end
Robert Chenff153962023-08-18 04:38:03 -040022 field WIFI_SAR_ID2 16 19
Robert Chen4a0b5992023-08-23 02:55:47 -040023 option INTEL_QUANDISO_LTE 0
24 option INTEL_QUANDISO_WIFI 1
25 option INTEL_QUANDISO360_LTE 2
26 option INTEL_QUANDISO360_WIFI 3
Robert Chenff153962023-08-18 04:38:03 -040027 option UNUSED 15
28 end
Robert Chen582a6ef2023-09-06 01:59:11 -040029 field AUDIO_AMP 20 21
30 option MAX98360A 0
31 option ALC1019 1
32 end
Robert Chenf151cd22023-10-03 03:58:22 -040033 field USB_WFC 22 23
34 option USB_WFC_ABSENT 0
35 option USB_WFC_PRESENT 1
36 end
Robert Chenff153962023-08-18 04:38:03 -040037end
38
Robert Chen02295db2023-08-17 04:23:49 -040039chip soc/intel/alderlake
Robert Chenff153962023-08-18 04:38:03 -040040 register "sagv" = "SaGv_Enabled"
Robert Chen02295db2023-08-17 04:23:49 -040041
Robert Chenff153962023-08-18 04:38:03 -040042 # EMMC Tx CMD Delay
43 # Refer to EDS-Vol2-42.3.7.
44 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
45 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
46 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
Robert Chen02295db2023-08-17 04:23:49 -040047
Robert Chenff153962023-08-18 04:38:03 -040048 # EMMC TX DATA Delay 1
49 # Refer to EDS-Vol2-42.3.8.
50 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
51 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
52 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
53
54 # EMMC TX DATA Delay 2
55 # Refer to EDS-Vol2-42.3.9.
56 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
57 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
58 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
59 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
60 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C272828"
61
62 # EMMC RX CMD/DATA Delay 1
63 # Refer to EDS-Vol2-42.3.10.
64 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
65 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
66 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
67 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
68 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C171733"
69
70 # EMMC RX CMD/DATA Delay 2
71 # Refer to EDS-Vol2-42.3.12.
72 # [17:16] stands for Rx Clock before Output Buffer,
73 # 00: Rx clock after output buffer,
74 # 01: Rx clock before output buffer,
75 # 10: Automatic selection based on working mode.
76 # 11: Reserved
77 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
78 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
79 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10024"
80
81 # EMMC Rx Strobe Delay
82 # Refer to EDS-Vol2-42.3.11.
83 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
84 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
85 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414"
86
87 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
88 # Bit 2 - C1 has a redriver which does SBU muxing.
89 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
90 register "tcss_aux_ori" = "1"
91
92 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
93
Robert Chenaea0c492023-08-24 04:06:40 -040094 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN
95 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Rear Camera
Robert Chenff153962023-08-18 04:38:03 -040096 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
97 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
98
Robert Chenaea0c492023-08-24 04:06:40 -040099 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN
Robert Chenff153962023-08-18 04:38:03 -0400100
101 # Configure external V1P05/Vnn/VnnSx Rails
102 register "ext_fivr_settings" = "{
103 .configure_ext_fivr = 1,
104 }"
105
106 # Intel Common SoC Config
107 #+-------------------+---------------------------+
108 #| Field | Value |
109 #+-------------------+---------------------------+
110 #| I2C0 | TPM. Early init is |
111 #| | required to set up a BAR |
112 #| | for TPM communication |
113 #| I2C1 | Touchscreen |
Robert Chen242bed22023-08-23 02:36:50 -0400114 #| I2C2 | P-sensor |
Robert Chenff153962023-08-18 04:38:03 -0400115 #| I2C3 | Audio |
116 #| I2C5 | Trackpad |
117 #+-------------------+---------------------------+
118 register "common_soc_config" = "{
119 .i2c[0] = {
120 .early_init = 1,
121 .speed = I2C_SPEED_FAST_PLUS,
122 .speed_config[0] = {
123 .speed = I2C_SPEED_FAST_PLUS,
124 .scl_lcnt = 56,
125 .scl_hcnt = 30,
126 .sda_hold = 7,
127 }
128 },
129 .i2c[1] = {
130 .speed = I2C_SPEED_FAST,
131 .speed_config[0] = {
132 .speed = I2C_SPEED_FAST,
133 .scl_lcnt = 158,
134 .scl_hcnt = 79,
135 .sda_hold = 30,
136 }
137 },
138 .i2c[2] = {
139 .speed = I2C_SPEED_FAST,
140 .speed_config[0] = {
141 .speed = I2C_SPEED_FAST,
142 .scl_lcnt = 158,
143 .scl_hcnt = 79,
144 .sda_hold = 7,
145 }
146 },
147 .i2c[3] = {
148 .speed = I2C_SPEED_FAST,
149 .speed_config[0] = {
150 .speed = I2C_SPEED_FAST,
151 .scl_lcnt = 158,
152 .scl_hcnt = 79,
153 .sda_hold = 7,
154 }
155 },
156 .i2c[5] = {
157 .speed = I2C_SPEED_FAST,
158 .speed_config[0] = {
159 .speed = I2C_SPEED_FAST,
160 .scl_lcnt = 158,
161 .scl_hcnt = 79,
162 .sda_hold = 40,
163 }
164 },
165 }"
166
167 device domain 0 on
168 device ref dtt on
169 chip drivers/intel/dptf
170 ## sensor information
171 register "options.tsr[0].desc" = ""CPU""
172 register "options.tsr[1].desc" = ""5V Regulator""
173 register "options.tsr[2].desc" = ""Charger""
174
175 # TODO: below values are initial reference values only
176 ## Passive Policy
177 register "policies.passive" = "{
178 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
179 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
180 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
181 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
182 }"
183
184 ## Critical Policy
185 register "policies.critical" = "{
186 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
187 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
188 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
189 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
190 }"
191
192 register "controls.power_limits" = "{
193 .pl1 = {
194 .min_power = 3000,
195 .max_power = 6000,
196 .time_window_min = 28 * MSECS_PER_SEC,
197 .time_window_max = 32 * MSECS_PER_SEC,
198 .granularity = 200
199 },
200 .pl2 = {
201 .min_power = 25000,
202 .max_power = 25000,
203 .time_window_min = 28 * MSECS_PER_SEC,
204 .time_window_max = 32 * MSECS_PER_SEC,
205 .granularity = 1000
206 }
207 }"
208
209 ## Charger Performance Control (Control, mA)
210 register "controls.charger_perf" = "{
211 [0] = { 255, 1700 },
212 [1] = { 24, 1500 },
213 [2] = { 16, 1000 },
214 [3] = { 8, 500 }
215 }"
216
217 device generic 0 on end
218 end
219 end
Robert Chenff153962023-08-18 04:38:03 -0400220 device ref cnvi_wifi on
221 chip drivers/wifi/generic
222 register "enable_cnvi_ddr_rfim" = "true"
223 device generic 0 on end
224 end
225 end
226 device ref i2c1 on
227 chip drivers/i2c/generic
228 register "hid" = ""ELAN0001""
229 register "desc" = ""ELAN Touchscreen""
230 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
231 register "detect" = "1"
232 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
233 register "reset_delay_ms" = "20"
234 register "reset_off_delay_ms" = "2"
235 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
236 register "stop_delay_ms" = "280"
237 register "stop_off_delay_ms" = "2"
238 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
239 register "enable_delay_ms" = "1"
240 register "has_power_resource" = "1"
241 device i2c 10 on end
242 end
243 chip drivers/i2c/hid
244 register "generic.hid" = ""ELAN2513""
245 register "generic.desc" = ""ELAN Touchscreen""
246 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
247 register "generic.detect" = "1"
248 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
249 register "generic.reset_delay_ms" = "20"
250 register "generic.reset_off_delay_ms" = "2"
251 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
252 register "generic.stop_delay_ms" = "280"
253 register "generic.stop_off_delay_ms" = "2"
254 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
255 register "generic.enable_delay_ms" = "1"
256 register "generic.has_power_resource" = "1"
257 register "hid_desc_reg_offset" = "0x01"
258 device i2c 15 on end
259 end
260 chip drivers/i2c/hid
261 register "generic.hid" = ""GTCH7503""
262 register "generic.desc" = ""G2TOUCH Touchscreen""
263 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
264 register "generic.detect" = "1"
265 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
266 register "generic.reset_delay_ms" = "50"
267 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
268 register "generic.enable_delay_ms" = "1"
269 register "generic.has_power_resource" = "1"
270 register "hid_desc_reg_offset" = "0x01"
271 device i2c 40 on end
272 end
273 chip drivers/generic/gpio_keys
274 register "name" = ""PENH""
275 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
276 register "key.wake_gpe" = "GPE0_DW2_15"
277 register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
278 register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
279 register "key.dev_name" = ""EJCT""
280 register "key.linux_code" = "SW_PEN_INSERTED"
281 register "key.linux_input_type" = "EV_SW"
282 register "key.label" = ""pen_eject""
283 device generic 0 on
284 probe STYLUS STYLUS_PRESENT
285 end
286 end
287 end
Robert Chen242bed22023-08-23 02:36:50 -0400288 device ref i2c2 on
289 chip drivers/i2c/sx9324
290 register "desc" = ""SAR Proximity Sensor""
291 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
292 register "speed" = "I2C_SPEED_FAST"
293 register "uid" = "1"
294 register "reg_gnrl_ctrl0" = "0x16"
295 register "reg_gnrl_ctrl1" = "0x21"
296 register "reg_afe_ctrl0" = "0x00"
297 register "reg_afe_ctrl1" = "0x10"
298 register "reg_afe_ctrl2" = "0x00"
299 register "reg_afe_ctrl3" = "0x00"
300 register "reg_afe_ctrl4" = "0x07"
301 register "reg_afe_ctrl5" = "0x00"
302 register "reg_afe_ctrl6" = "0x00"
303 register "reg_afe_ctrl7" = "0x07"
304 register "reg_afe_ctrl8" = "0x12"
305 register "reg_afe_ctrl9" = "0x0f"
306 register "reg_prox_ctrl0" = "0x12"
307 register "reg_prox_ctrl1" = "0x12"
308 register "reg_prox_ctrl2" = "0x90"
309 register "reg_prox_ctrl3" = "0x60"
310 register "reg_prox_ctrl4" = "0x0c"
311 register "reg_prox_ctrl5" = "0x12"
312 register "reg_prox_ctrl6" = "0x3c"
313 register "reg_prox_ctrl7" = "0x58"
314 register "reg_adv_ctrl0" = "0x00"
315 register "reg_adv_ctrl1" = "0x00"
316 register "reg_adv_ctrl2" = "0x00"
317 register "reg_adv_ctrl3" = "0x00"
318 register "reg_adv_ctrl4" = "0x00"
319 register "reg_adv_ctrl5" = "0x05"
320 register "reg_adv_ctrl6" = "0x00"
321 register "reg_adv_ctrl7" = "0x00"
322 register "reg_adv_ctrl8" = "0x00"
323 register "reg_adv_ctrl9" = "0x00"
324 register "reg_adv_ctrl10" = "0x5c"
325 register "reg_adv_ctrl11" = "0x52"
326 register "reg_adv_ctrl12" = "0xb5"
327 register "reg_adv_ctrl13" = "0x00"
328 register "reg_adv_ctrl14" = "0x80"
329 register "reg_adv_ctrl15" = "0x0c"
330 register "reg_adv_ctrl16" = "0x38"
331 register "reg_adv_ctrl17" = "0x56"
332 register "reg_adv_ctrl18" = "0x33"
333 register "reg_adv_ctrl19" = "0xf0"
334 register "reg_adv_ctrl20" = "0xf0"
335 device i2c 28 on
Robert Chen50829632023-11-28 02:24:58 -0500336 probe DB_USB DB_LTE
Robert Chen242bed22023-08-23 02:36:50 -0400337 probe DB_USB DB_1C_LTE
338 end
339 end
340 end
Robert Chenff153962023-08-18 04:38:03 -0400341 device ref i2c3 on
342 chip drivers/i2c/generic
343 register "hid" = ""RTL5682""
344 register "name" = ""RT58""
345 register "desc" = ""Headset Codec""
346 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
347 # Set the jd_src to RT5668_JD1 for jack detection
348 register "property_count" = "1"
349 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
350 register "property_list[0].name" = ""realtek,jd-src""
351 register "property_list[0].integer" = "1"
352 device i2c 1a on end
353 end
Robert Chen582a6ef2023-09-06 01:59:11 -0400354 chip drivers/generic/alc1015
355 register "hid" = ""RTL1019""
356 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
357 device generic 0 on
358 probe AUDIO_AMP ALC1019
359 end
360 end
Robert Chenff153962023-08-18 04:38:03 -0400361 end
362 device ref i2c5 on
363 chip drivers/i2c/generic
364 register "hid" = ""ELAN0000""
365 register "desc" = ""ELAN Touchpad""
366 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
367 register "wake" = "GPE0_DW2_14"
368 register "detect" = "1"
369 device i2c 15 on end
370 end
371 chip drivers/i2c/hid
372 register "generic.hid" = ""SYNA0000""
373 register "generic.cid" = ""ACPI0C50""
374 register "generic.desc" = ""Synaptics Touchpad""
375 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
376 register "generic.wake" = "GPE0_DW2_14"
377 register "generic.detect" = "1"
378 register "hid_desc_reg_offset" = "0x20"
379 device i2c 0x2c on end
380 end
381 end
382 device ref hda on
383 chip drivers/generic/max98357a
384 register "hid" = ""MX98360A""
385 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
386 register "sdmode_delay" = "5"
Robert Chen582a6ef2023-09-06 01:59:11 -0400387 device generic 0 on
388 probe AUDIO_AMP MAX98360A
389 end
Robert Chenff153962023-08-18 04:38:03 -0400390 end
391 end
392 device ref pcie_rp4 on
393 # PCIe 4 WLAN
394 register "pch_pcie_rp[PCH_RP(4)]" = "{
395 .clk_src = 2,
396 .clk_req = 2,
397 .flags = PCIE_RP_LTR | PCIE_RP_AER,
398 }"
399 chip drivers/wifi/generic
400 register "wake" = "GPE0_DW1_03"
401 register "add_acpi_dma_property" = "true"
Matt DeVillierf4938572023-11-01 18:50:25 -0500402 device generic 0 on end
Robert Chenff153962023-08-18 04:38:03 -0400403 end
404 end
Robert Chen4a0b5992023-08-23 02:55:47 -0400405 device ref pcie_rp7 on
406 # Enable SD Card PCIe 7 using clk 3
407 register "pch_pcie_rp[PCH_RP(7)]" = "{
408 .clk_src = 3,
409 .clk_req = 3,
410 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
411 }"
412 chip soc/intel/common/block/pcie/rtd3
413 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
414 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
415 register "srcclk_pin" = "3"
416 device generic 0 on end
417 end
418 probe SD_CARD SD_PRESENT
419 end
Robert Chenff153962023-08-18 04:38:03 -0400420 device ref emmc on end
421 device ref ish on
422 chip drivers/intel/ish
423 register "add_acpi_dma_property" = "true"
424 device generic 0 on end
425 end
426 end
427 device ref ufs on end
428 device ref pch_espi on
429 chip ec/google/chromeec
430 use conn0 as mux_conn[0]
431 use conn1 as mux_conn[1]
432 device pnp 0c09.0 on end
433 end
434 end
435 device ref pmc hidden
436 chip drivers/intel/pmc_mux
437 device generic 0 on
438 chip drivers/intel/pmc_mux/conn
439 use usb2_port1 as usb2_port
440 use tcss_usb3_port1 as usb3_port
441 device generic 0 alias conn0 on end
442 end
443 chip drivers/intel/pmc_mux/conn
444 use usb2_port2 as usb2_port
445 use tcss_usb3_port2 as usb3_port
Robert Chen39b19f22023-11-20 01:39:00 -0500446 device generic 1 alias conn1 on
447 probe DB_USB DB_1C_1A
Robert Chen39b19f22023-11-20 01:39:00 -0500448 probe DB_USB DB_1C_LTE
449 end
Robert Chenff153962023-08-18 04:38:03 -0400450 end
451 end
452 end
453 end
454 device ref tcss_xhci on
455 chip drivers/usb/acpi
456 device ref tcss_root_hub on
457 chip drivers/usb/acpi
458 register "desc" = ""USB3 Type-C Port C0 (MLB)""
459 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
460 register "use_custom_pld" = "true"
461 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
462 device ref tcss_usb3_port1 on end
463 end
464 chip drivers/usb/acpi
465 register "desc" = ""USB3 Type-C Port C1 (DB)""
466 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
467 register "use_custom_pld" = "true"
468 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
Robert Chen39b19f22023-11-20 01:39:00 -0500469 device ref tcss_usb3_port2 on
470 probe DB_USB DB_1C_1A
Robert Chen39b19f22023-11-20 01:39:00 -0500471 probe DB_USB DB_1C_LTE
472 end
Robert Chenff153962023-08-18 04:38:03 -0400473 end
474 end
475 end
476 end
477 device ref xhci on
478 chip drivers/usb/acpi
479 device ref xhci_root_hub on
480 chip drivers/usb/acpi
481 register "desc" = ""USB2 Type-C Port C0 (MLB)""
482 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
483 register "use_custom_pld" = "true"
484 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
485 device ref usb2_port1 on end
486 end
487 chip drivers/usb/acpi
488 register "desc" = ""USB2 Type-C Port C1 (DB)""
489 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
490 register "use_custom_pld" = "true"
491 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
Robert Chen39b19f22023-11-20 01:39:00 -0500492 device ref usb2_port2 on
493 probe DB_USB DB_1C_1A
Robert Chen39b19f22023-11-20 01:39:00 -0500494 probe DB_USB DB_1C_LTE
495 end
Robert Chenff153962023-08-18 04:38:03 -0400496 end
497 chip drivers/usb/acpi
498 register "desc" = ""USB2 Type-A Port A0 (MLB)""
499 register "type" = "UPC_TYPE_A"
500 register "use_custom_pld" = "true"
501 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
502 device ref usb2_port3 on end
503 end
504 chip drivers/usb/acpi
Robert Chenaea0c492023-08-24 04:06:40 -0400505 register "desc" = ""USB2 Type-A Port A1 (DB)""
Robert Chenff153962023-08-18 04:38:03 -0400506 register "type" = "UPC_TYPE_A"
507 register "use_custom_pld" = "true"
508 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
Robert Chenaea0c492023-08-24 04:06:40 -0400509 device ref usb2_port4 on
510 probe DB_USB DB_1C_1A
511 end
Robert Chenff153962023-08-18 04:38:03 -0400512 end
513 chip drivers/usb/acpi
514 register "desc" = ""USB2 WWAN""
515 register "type" = "UPC_TYPE_INTERNAL"
Robert Chenaea0c492023-08-24 04:06:40 -0400516 device ref usb2_port4 on
Robert Chenff153962023-08-18 04:38:03 -0400517 probe DB_USB DB_1C_LTE
518 end
519 end
520 chip drivers/usb/acpi
521 register "desc" = ""USB2 UFC""
522 register "type" = "UPC_TYPE_INTERNAL"
523 device ref usb2_port6 on end
524 end
525 chip drivers/usb/acpi
Robert Chenaea0c492023-08-24 04:06:40 -0400526 register "desc" = ""USB2 WF Camera""
527 register "type" = "UPC_TYPE_INTERNAL"
528 device ref usb2_port7 on
Robert Chenf151cd22023-10-03 03:58:22 -0400529 probe USB_WFC USB_WFC_PRESENT
Robert Chenaea0c492023-08-24 04:06:40 -0400530 end
531 end
532 chip drivers/usb/acpi
Robert Chenff153962023-08-18 04:38:03 -0400533 register "desc" = ""USB2 Bluetooth""
534 register "type" = "UPC_TYPE_INTERNAL"
535 register "reset_gpio" =
536 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
537 device ref usb2_port8 on end
538 end
539 chip drivers/usb/acpi
540 register "desc" = ""CNVi Bluetooth""
541 register "type" = "UPC_TYPE_INTERNAL"
542 register "reset_gpio" =
543 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
544 device ref usb2_port10 on end
545 end
546 chip drivers/usb/acpi
547 register "desc" = ""USB3 Type-A Port A0 (MLB)""
548 register "type" = "UPC_TYPE_USB3_A"
549 register "use_custom_pld" = "true"
550 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
551 device ref usb3_port1 on end
552 end
553 chip drivers/usb/acpi
554 register "desc" = ""USB3 Type-A Port A1 (DB)""
555 register "type" = "UPC_TYPE_USB3_A"
556 register "use_custom_pld" = "true"
557 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
Robert Chenaea0c492023-08-24 04:06:40 -0400558 device ref usb3_port2 on
559 probe DB_USB DB_1C_1A
560 end
Robert Chenff153962023-08-18 04:38:03 -0400561 end
562 chip drivers/usb/acpi
563 register "desc" = ""USB3 WWAN""
564 register "type" = "UPC_TYPE_INTERNAL"
Robert Chenaea0c492023-08-24 04:06:40 -0400565 device ref usb3_port2 on
Robert Chen50829632023-11-28 02:24:58 -0500566 probe DB_USB DB_LTE
Robert Chenff153962023-08-18 04:38:03 -0400567 probe DB_USB DB_1C_LTE
568 end
569 end
570 end
571 end
572 end
573 end
Robert Chen02295db2023-08-17 04:23:49 -0400574end