blob: 86172ba1f17fcb2fcd5fffc9f01fd367d8c35a77 [file] [log] [blame]
Frank Vibrans69da1b62011-02-14 19:04:45 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <arch/io.h>
24#include <boot/tables.h>
25#include <cpu/x86/msr.h>
Frank Vibrans69da1b62011-02-14 19:04:45 +000026#include <device/pci_def.h>
zbaof543c7b2012-04-13 13:42:46 +080027#include <southbridge/amd/sb800/sb800.h>
28#include <arch/acpi.h>
Frank Vibrans69da1b62011-02-14 19:04:45 +000029#include "chip.h"
zbaof543c7b2012-04-13 13:42:46 +080030#include "BiosCallOuts.h"
31#include <cpu/amd/agesa/s3_resume.h>
32#include <cpu/amd/mtrr.h>
Frank Vibrans69da1b62011-02-14 19:04:45 +000033
efdesign98d7a696d2011-09-15 15:24:26 -060034void set_pcie_reset(void);
35void set_pcie_dereset(void);
Frank Vibrans69da1b62011-02-14 19:04:45 +000036
37/**
38 * TODO
39 * SB CIMx callback
40 */
41void set_pcie_reset(void)
42{
43}
44
45/**
46 * TODO
47 * mainboard specific SB CIMx callback
48 */
49void set_pcie_dereset(void)
50{
51}
52
Frank Vibrans69da1b62011-02-14 19:04:45 +000053
54/*************************************************
55* enable the dedicated function in persimmon board.
56*************************************************/
57static void persimmon_enable(device_t dev)
58{
Scott Duplichan8c462632011-05-15 22:10:15 +000059 printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
60
zbaof543c7b2012-04-13 13:42:46 +080061/*
62 * The mainboard is the first place that we get control in ramstage. Check
63 * for S3 resume and call the approriate AGESA/CIMx resume functions.
64 */
Patrick Georgie1667822012-05-05 15:29:32 +020065#if CONFIG_HAVE_ACPI_RESUME
zbaof543c7b2012-04-13 13:42:46 +080066 acpi_slp_type = acpi_get_sleep_type();
67#endif
68
Kyösti Mälkki55fff9302012-07-11 08:02:39 +030069 setup_uma_memory();
Frank Vibrans69da1b62011-02-14 19:04:45 +000070
71}
72
73int add_mainboard_resources(struct lb_memory *mem)
74{
Frank Vibrans69da1b62011-02-14 19:04:45 +000075 return 0;
76}
zbaof543c7b2012-04-13 13:42:46 +080077
Frank Vibrans69da1b62011-02-14 19:04:45 +000078struct chip_operations mainboard_ops = {
Scott Duplichan8c462632011-05-15 22:10:15 +000079 CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
Frank Vibrans69da1b62011-02-14 19:04:45 +000080 .enable_dev = persimmon_enable,
81};