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review.coreboot.org / coreboot / 4f8ff240dd45fc568b05bb17bea5afca7a8ce75c / . / src / southbridge / intel / i82801ix / smbus.h
blob: bcc758700de0a43a18230f2f14d2fbff13c50994 [file] [log] [blame]
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
5 * Copyright (C) 2009 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Patrick Georgie72a8a32012-11-06 11:05:09 +0100[diff] [blame]15 */
16
17#include <device/smbus_def.h>
18#include "i82801ix.h"
19
20static void smbus_delay(void)
21{
22 inb(0x80);
23}
24
25static int smbus_wait_until_ready(u16 smbus_base)
26{
27 unsigned loops = SMBUS_TIMEOUT;
28 unsigned char byte;
29 do {
30 smbus_delay();
31 if (--loops == 0)
32 break;
33 byte = inb(smbus_base + SMBHSTSTAT);
34 } while (byte & 1);
35 return loops ? 0 : -1;
36}
37
38static int smbus_wait_until_done(u16 smbus_base)
39{
40 unsigned loops = SMBUS_TIMEOUT;
41 unsigned char byte;
42 do {
43 smbus_delay();
44 if (--loops == 0)
45 break;
46 byte = inb(smbus_base + SMBHSTSTAT);
47 } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
48 return loops ? 0 : -1;
49}
50
51static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
52{
53 unsigned char global_status_register;
54 unsigned char byte;
55
56 if (smbus_wait_until_ready(smbus_base) < 0) {
57 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
58 }
59 /* Setup transaction */
60 /* Disable interrupts */
61 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
62 /* Set the device I'm talking too */
63 outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
64 /* Set the command/address... */
65 outb(address & 0xff, smbus_base + SMBHSTCMD);
66 /* Set up for a byte data read */
67 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
68 (smbus_base + SMBHSTCTL));
69 /* Clear any lingering errors, so the transaction will run */
70 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
71
72 /* Clear the data byte... */
73 outb(0, smbus_base + SMBHSTDAT0);
74
75 /* Start the command */
76 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
77 smbus_base + SMBHSTCTL);
78
79 /* Poll for transaction completion */
80 if (smbus_wait_until_done(smbus_base) < 0) {
81 return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
82 }
83
84 global_status_register = inb(smbus_base + SMBHSTSTAT);
85
86 /* Ignore the "In Use" status... */
87 global_status_register &= ~(3 << 5);
88
89 /* Read results of transaction */
90 byte = inb(smbus_base + SMBHSTDAT0);
91 if (global_status_register != (1 << 1)) {
92 return SMBUS_ERROR;
93 }
94 return byte;
95}
Vladimir Serbinenkocaf1df02014-08-01 02:49:27 +0200[diff] [blame]96
97#ifndef __PRE_RAM__
98static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
99{
100 unsigned char global_status_register;
101
102 if (smbus_wait_until_ready(smbus_base) < 0)
103 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
104
105 /* Setup transaction */
106 /* Disable interrupts */
107 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
108 /* Set the device I'm talking too */
109 outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
110 /* Set the command/address... */
111 outb(address & 0xff, smbus_base + SMBHSTCMD);
112 /* Set up for a byte data read */
113 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
114 (smbus_base + SMBHSTCTL));
115 /* Clear any lingering errors, so the transaction will run */
116 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
117
118 /* Clear the data byte... */
119 outb(data, smbus_base + SMBHSTDAT0);
120
121 /* Start the command */
122 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
123 smbus_base + SMBHSTCTL);
124
125 /* Poll for transaction completion */
126 if (smbus_wait_until_done(smbus_base) < 0)
127 return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
128
129 global_status_register = inb(smbus_base + SMBHSTSTAT);
130
131 /* Ignore the "In Use" status... */
132 global_status_register &= ~(3 << 5);
133
134 /* Read results of transaction */
135 if (global_status_register != (1 << 1))
136 return SMBUS_ERROR;
137
138 return 0;
139}
140#endif