Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
David Wu | 456f8dc | 2020-09-02 14:54:01 +0800 | [diff] [blame] | 2 | register "tcc_offset" = "5" # TCC of 95C |
| 3 | |
| 4 | register "power_limits_config" = "{ |
| 5 | .tdp_pl1_override = 15, |
| 6 | .tdp_pl2_override = 51, |
| 7 | }" |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 8 | |
| 9 | # Auto-switch between X4 NVMe and X2 NVMe. |
| 10 | register "TetonGlacierMode" = "1" |
| 11 | |
| 12 | register "SerialIoDevMode" = "{ |
| 13 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 14 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 15 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 16 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 17 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
Matt DeVillier | 8facfa8 | 2024-01-21 20:48:26 -0600 | [diff] [blame] | 18 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 19 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
Matt DeVillier | 8facfa8 | 2024-01-21 20:48:26 -0600 | [diff] [blame] | 20 | [PchSerialIoIndexSPI1] = PchSerialIoDisabled, |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 21 | [PchSerialIoIndexSPI2] = PchSerialIoDisabled, |
| 22 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| 23 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 24 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 25 | }" |
| 26 | |
| 27 | # USB configuration |
| 28 | register "usb2_ports[0]" = "{ |
| 29 | .enable = 1, |
| 30 | .ocpin = OC2, |
| 31 | .tx_bias = USB2_BIAS_0MV, |
| 32 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 33 | .pre_emp_bias = USB2_BIAS_11P25MV, |
| 34 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 35 | }" # Type-A Port 2 |
| 36 | register "usb2_ports[1]" = "{ |
| 37 | .enable = 1, |
| 38 | .ocpin = OC1, |
| 39 | .tx_bias = USB2_BIAS_0MV, |
| 40 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 41 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 42 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 43 | }" # Type-A Port 1 |
| 44 | register "usb2_ports[2]" = "{ |
| 45 | .enable = 1, |
| 46 | .ocpin = OC3, |
| 47 | .tx_bias = USB2_BIAS_0MV, |
| 48 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 49 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 50 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 51 | }" # Type-A Port 3 |
| 52 | register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port |
| 53 | register "usb2_ports[4]" = "{ |
| 54 | .enable = 1, |
| 55 | .ocpin = OC_SKIP, |
| 56 | .tx_bias = USB2_BIAS_0MV, |
| 57 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 58 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 59 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 60 | }" # Type-A Port 4 |
| 61 | register "usb2_ports[5]" = "{ |
| 62 | .enable = 1, |
| 63 | .ocpin = OC0, |
| 64 | .tx_bias = USB2_BIAS_0MV, |
| 65 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 66 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 67 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 68 | }" # Type-A port 0 |
Tim Chen | ba26aa8 | 2020-06-24 14:26:03 +0800 | [diff] [blame] | 69 | register "usb2_ports[6]" = "{ |
| 70 | .enable = 1, |
| 71 | .ocpin = OC_SKIP, |
| 72 | .tx_bias = USB2_BIAS_0MV, |
| 73 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 74 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 75 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 76 | }" # PL2303 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 77 | register "usb2_ports[9]" = "{ |
| 78 | .enable = 1, |
| 79 | .ocpin = OC_SKIP, |
| 80 | .tx_bias = USB2_BIAS_0MV, |
| 81 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 82 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 83 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 84 | }" # BT |
| 85 | |
Tim Chen | 24a6184 | 2020-07-15 20:19:10 +0800 | [diff] [blame] | 86 | register "usb3_ports[0]" = "{ |
| 87 | .enable = 1, |
| 88 | .ocpin = OC2, |
| 89 | .tx_de_emp = 0x00, |
| 90 | .tx_downscale_amp = 0x00, |
| 91 | .gen2_tx_rate0_uniq_tran_enable = 0, |
| 92 | .gen2_tx_rate0_uniq_tran = 0x00, |
| 93 | .gen2_tx_rate1_uniq_tran_enable = 0, |
| 94 | .gen2_tx_rate1_uniq_tran = 0x00, |
| 95 | .gen2_tx_rate2_uniq_tran_enable = 1, |
| 96 | .gen2_tx_rate2_uniq_tran = 0x4c, |
| 97 | .gen2_tx_rate3_uniq_tran_enable = 0, |
| 98 | .gen2_tx_rate3_uniq_tran = 0x00, |
| 99 | .gen2_rx_tuning_enable = 0x0f, |
| 100 | .gen2_rx_tuning_params = 0x45, |
| 101 | .gen2_rx_filter_sel = 0x44, |
| 102 | }" # Type-A Port 2 |
| 103 | register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 |
| 104 | register "usb3_ports[2]" = "{ |
| 105 | .enable = 1, |
| 106 | .ocpin = OC1, |
| 107 | .tx_de_emp = 0x00, |
| 108 | .tx_downscale_amp = 0x00, |
| 109 | .gen2_tx_rate0_uniq_tran_enable = 0, |
| 110 | .gen2_tx_rate0_uniq_tran = 0x00, |
| 111 | .gen2_tx_rate1_uniq_tran_enable = 0, |
| 112 | .gen2_tx_rate1_uniq_tran = 0x00, |
| 113 | .gen2_tx_rate2_uniq_tran_enable = 1, |
| 114 | .gen2_tx_rate2_uniq_tran = 0x4c, |
| 115 | .gen2_tx_rate3_uniq_tran_enable = 0, |
| 116 | .gen2_tx_rate3_uniq_tran = 0x00, |
| 117 | .gen2_rx_tuning_enable = 0x0f, |
| 118 | .gen2_rx_tuning_params = 0x3d, |
| 119 | .gen2_rx_filter_sel = 0x44, |
| 120 | }" # Type-A Port 1 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 121 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C |
Tim Chen | 24a6184 | 2020-07-15 20:19:10 +0800 | [diff] [blame] | 122 | register "usb3_ports[4]" = "{ |
| 123 | .enable = 1, |
| 124 | .ocpin = OC0, |
| 125 | .tx_de_emp = 0x00, |
| 126 | .tx_downscale_amp = 0x00, |
| 127 | .gen2_tx_rate0_uniq_tran_enable = 0, |
| 128 | .gen2_tx_rate0_uniq_tran = 0x00, |
| 129 | .gen2_tx_rate1_uniq_tran_enable = 0, |
| 130 | .gen2_tx_rate1_uniq_tran = 0x00, |
| 131 | .gen2_tx_rate2_uniq_tran_enable = 1, |
| 132 | .gen2_tx_rate2_uniq_tran = 0x4c, |
| 133 | .gen2_tx_rate3_uniq_tran_enable = 0, |
| 134 | .gen2_tx_rate3_uniq_tran = 0x00, |
| 135 | .gen2_rx_tuning_enable = 0x0f, |
| 136 | .gen2_rx_tuning_params = 0x45, |
| 137 | .gen2_rx_filter_sel = 0x44, |
| 138 | }" # Type-A Port 0 |
| 139 | register "usb3_ports[5]" = "{ |
| 140 | .enable = 1, |
| 141 | .ocpin = OC_SKIP, |
| 142 | .tx_de_emp = 0x00, |
| 143 | .tx_downscale_amp = 0x00, |
| 144 | .gen2_tx_rate0_uniq_tran_enable = 0, |
| 145 | .gen2_tx_rate0_uniq_tran = 0x00, |
| 146 | .gen2_tx_rate1_uniq_tran_enable = 0, |
| 147 | .gen2_tx_rate1_uniq_tran = 0x00, |
| 148 | .gen2_tx_rate2_uniq_tran_enable = 1, |
| 149 | .gen2_tx_rate2_uniq_tran = 0x4c, |
| 150 | .gen2_tx_rate3_uniq_tran_enable = 0, |
| 151 | .gen2_tx_rate3_uniq_tran = 0x00, |
| 152 | .gen2_rx_tuning_enable = 0x0f, |
| 153 | .gen2_rx_tuning_params = 0x45, |
| 154 | .gen2_rx_filter_sel = 0x44, |
| 155 | }" # Type-A Port 4 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 156 | |
Edward O'Callaghan | dc7b944 | 2020-07-01 18:46:16 +1000 | [diff] [blame] | 157 | # Bitmap for Wake Enable on USB attach/detach |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 158 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 159 | USB_PORT_WAKE_ENABLE(2) | |
| 160 | USB_PORT_WAKE_ENABLE(3) | |
| 161 | USB_PORT_WAKE_ENABLE(5) | |
Edward O'Callaghan | dc7b944 | 2020-07-01 18:46:16 +1000 | [diff] [blame] | 162 | USB_PORT_WAKE_ENABLE(6)" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 163 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 164 | USB_PORT_WAKE_ENABLE(2) | |
| 165 | USB_PORT_WAKE_ENABLE(3) | |
| 166 | USB_PORT_WAKE_ENABLE(5) | |
Edward O'Callaghan | dc7b944 | 2020-07-01 18:46:16 +1000 | [diff] [blame] | 167 | USB_PORT_WAKE_ENABLE(6)" |
| 168 | |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 169 | # Enable eMMC HS400 |
| 170 | register "ScsEmmcHs400Enabled" = "1" |
| 171 | |
| 172 | # EMMC Tx CMD Delay |
| 173 | # Refer to EDS-Vol2-14.3.7. |
| 174 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 175 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 176 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 177 | |
| 178 | # EMMC TX DATA Delay 1 |
| 179 | # Refer to EDS-Vol2-14.3.8. |
| 180 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 181 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 182 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" |
| 183 | |
| 184 | # EMMC TX DATA Delay 2 |
| 185 | # Refer to EDS-Vol2-14.3.9. |
| 186 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 187 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 188 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 189 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 190 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" |
| 191 | |
| 192 | # EMMC RX CMD/DATA Delay 1 |
| 193 | # Refer to EDS-Vol2-14.3.10. |
| 194 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 195 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 196 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 197 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 198 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" |
| 199 | |
| 200 | # EMMC RX CMD/DATA Delay 2 |
| 201 | # Refer to EDS-Vol2-14.3.12. |
| 202 | # [17:16] stands for Rx Clock before Output Buffer, |
| 203 | # 00: Rx clock after output buffer, |
| 204 | # 01: Rx clock before output buffer, |
| 205 | # 10: Automatic selection based on working mode. |
| 206 | # 11: Reserved |
| 207 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 208 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 209 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" |
| 210 | |
| 211 | # EMMC Rx Strobe Delay |
| 212 | # Refer to EDS-Vol2-14.3.11. |
| 213 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 214 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 215 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" |
| 216 | |
| 217 | # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. |
| 218 | register "PchHdaAudioLinkSsp1" = "0" |
| 219 | register "PchHdaAudioLinkDmic0" = "0" |
| 220 | |
| 221 | # Intel Common SoC Config |
| 222 | #+-------------------+---------------------------+ |
| 223 | #| Field | Value | |
| 224 | #+-------------------+---------------------------+ |
| 225 | #| GSPI0 | cr50 TPM. Early init is | |
| 226 | #| | required to set up a BAR | |
| 227 | #| | for TPM communication | |
| 228 | #| | before memory is up | |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 229 | #| I2C2 | PS175 | |
| 230 | #| I2C3 | MST | |
| 231 | #| I2C4 | Audio | |
| 232 | #+-------------------+---------------------------+ |
| 233 | register "common_soc_config" = "{ |
| 234 | .gspi[0] = { |
| 235 | .speed_mhz = 1, |
| 236 | .early_init = 1, |
| 237 | }, |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 238 | .i2c[2] = { |
| 239 | .speed = I2C_SPEED_FAST, |
| 240 | .rise_time_ns = 60, |
| 241 | .fall_time_ns = 60, |
| 242 | }, |
| 243 | .i2c[3] = { |
| 244 | .speed = I2C_SPEED_FAST, |
| 245 | .rise_time_ns = 60, |
| 246 | .fall_time_ns = 60, |
| 247 | }, |
| 248 | .i2c[4] = { |
| 249 | .speed = I2C_SPEED_FAST, |
| 250 | .rise_time_ns = 60, |
| 251 | .fall_time_ns = 60, |
| 252 | }, |
| 253 | }" |
| 254 | |
| 255 | # PCIe port 7 for LAN |
| 256 | register "PcieRpEnable[6]" = "1" |
| 257 | register "PcieRpLtrEnable[6]" = "1" |
| 258 | # PCIe port 11 (x2) for NVMe hybrid storage devices |
| 259 | register "PcieRpEnable[10]" = "1" |
| 260 | register "PcieRpLtrEnable[10]" = "1" |
| 261 | # Uses CLK SRC 0 |
| 262 | register "PcieClkSrcUsage[0]" = "6" |
| 263 | register "PcieClkSrcClkReq[0]" = "0" |
| 264 | |
| 265 | # GPIO for SD card detect |
| 266 | register "sdcard_cd_gpio" = "vSD3_CD_B" |
| 267 | |
| 268 | # SATA port 1 Gen3 Strength |
| 269 | # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB |
| 270 | register "sata_port[1].TxGen3DeEmphEnable" = "1" |
| 271 | register "sata_port[1].TxGen3DeEmph" = "0x20" |
| 272 | |
| 273 | device domain 0 on |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 274 | device ref dptf on |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 275 | chip drivers/intel/dptf |
| 276 | ## Passive Policy |
David Wu | 456f8dc | 2020-09-02 14:54:01 +0800 | [diff] [blame] | 277 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" |
David Wu | 006acd3 | 2020-09-25 16:06:17 +0800 | [diff] [blame] | 278 | register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 73, 60000)" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 279 | |
| 280 | ## Critical Policy |
| 281 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" |
David Wu | 299cb4b | 2020-09-08 15:30:29 +0800 | [diff] [blame] | 282 | register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 283 | |
| 284 | ## Power Limits Control |
| 285 | # 10-15W PL1 in 200mW increments, avg over 28-32s interval |
David Wu | 456f8dc | 2020-09-02 14:54:01 +0800 | [diff] [blame] | 286 | # 15-51W PL2 in 1000mW increments, avg over 28-32s interval |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 287 | register "controls.power_limits.pl1" = "{ |
| 288 | .min_power = 10000, |
| 289 | .max_power = 15000, |
| 290 | .time_window_min = 28 * MSECS_PER_SEC, |
| 291 | .time_window_max = 32 * MSECS_PER_SEC, |
| 292 | .granularity = 200,}" |
| 293 | register "controls.power_limits.pl2" = "{ |
David Wu | 456f8dc | 2020-09-02 14:54:01 +0800 | [diff] [blame] | 294 | .min_power = 15000, |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 295 | .max_power = 51000, |
| 296 | .time_window_min = 28 * MSECS_PER_SEC, |
| 297 | .time_window_max = 32 * MSECS_PER_SEC, |
| 298 | .granularity = 1000,}" |
| 299 | |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 300 | device generic 0 on end |
| 301 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 302 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 303 | device ref xhci on |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 304 | chip drivers/usb/acpi |
| 305 | device usb 0.0 on |
| 306 | chip drivers/usb/acpi |
| 307 | register "desc" = ""USB2 Type-A Front Left"" |
| 308 | register "type" = "UPC_TYPE_A" |
| 309 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 310 | device usb 2.0 on end |
| 311 | end |
| 312 | chip drivers/usb/acpi |
| 313 | register "desc" = ""USB2 Type-C Port Rear"" |
| 314 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 315 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 316 | device usb 2.1 on end |
| 317 | end |
| 318 | chip drivers/usb/acpi |
| 319 | register "desc" = ""USB2 Type-A Front Right"" |
| 320 | register "type" = "UPC_TYPE_A" |
| 321 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 322 | device usb 2.2 on end |
| 323 | end |
| 324 | chip drivers/usb/acpi |
| 325 | register "desc" = ""USB2 Type-A Rear Right"" |
| 326 | register "type" = "UPC_TYPE_A" |
| 327 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 328 | device usb 2.3 on end |
| 329 | end |
| 330 | chip drivers/usb/acpi |
| 331 | register "desc" = ""USB2 Type-A Rear Middle"" |
| 332 | register "type" = "UPC_TYPE_A" |
| 333 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 334 | device usb 2.4 on end |
| 335 | end |
| 336 | chip drivers/usb/acpi |
| 337 | register "desc" = ""USB2 Type-A Rear Left"" |
| 338 | register "type" = "UPC_TYPE_A" |
| 339 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 340 | device usb 2.5 on end |
| 341 | end |
| 342 | chip drivers/usb/acpi |
| 343 | device usb 2.6 off end |
| 344 | end |
| 345 | chip drivers/usb/acpi |
| 346 | register "desc" = ""USB3 Type-A Front Left"" |
| 347 | register "type" = "UPC_TYPE_USB3_A" |
| 348 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 349 | device usb 3.0 on end |
| 350 | end |
| 351 | chip drivers/usb/acpi |
| 352 | register "desc" = ""USB3 Type-A Front Right"" |
| 353 | register "type" = "UPC_TYPE_USB3_A" |
| 354 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 355 | device usb 3.1 on end |
| 356 | end |
| 357 | chip drivers/usb/acpi |
| 358 | register "desc" = ""USB3 Type-A Rear Right"" |
| 359 | register "type" = "UPC_TYPE_USB3_A" |
| 360 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 361 | device usb 3.2 on end |
| 362 | end |
| 363 | chip drivers/usb/acpi |
| 364 | register "desc" = ""USB3 Type-C Rear"" |
| 365 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 366 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 367 | device usb 3.3 on end |
| 368 | end |
| 369 | chip drivers/usb/acpi |
| 370 | register "desc" = ""USB3 Type-A Rear Left"" |
| 371 | register "type" = "UPC_TYPE_USB3_A" |
| 372 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 373 | device usb 3.4 on end |
| 374 | end |
| 375 | chip drivers/usb/acpi |
| 376 | register "desc" = ""USB3 Type-A Rear Middle"" |
| 377 | register "type" = "UPC_TYPE_USB3_A" |
| 378 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 379 | device usb 3.5 on end |
| 380 | end |
| 381 | end |
| 382 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 383 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 384 | device ref i2c2 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 385 | # PCON PS175 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 386 | chip drivers/i2c/generic |
| 387 | register "hid" = ""1AF80175"" |
| 388 | register "name" = ""PS17"" |
| 389 | register "desc" = ""Parade PS175"" |
Matt DeVillier | 4f86e1d | 2023-09-20 16:30:06 -0500 | [diff] [blame^] | 390 | device i2c 4a hidden end |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 391 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 392 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 393 | device ref i2c3 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 394 | # Realtek RTD2142 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 395 | chip drivers/i2c/generic |
| 396 | register "hid" = ""10EC2142"" |
| 397 | register "name" = ""RTD2"" |
| 398 | register "desc" = ""Realtek RTD2142"" |
Matt DeVillier | 4f86e1d | 2023-09-20 16:30:06 -0500 | [diff] [blame^] | 399 | device i2c 4a hidden end |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 400 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 401 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 402 | device ref i2c4 on |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 403 | chip drivers/i2c/generic |
| 404 | register "hid" = ""10EC5682"" |
| 405 | register "name" = ""RT58"" |
| 406 | register "desc" = ""Realtek RT5682"" |
| 407 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" |
| 408 | register "property_count" = "1" |
| 409 | # Set the jd_src to RT5668_JD1 for jack detection |
| 410 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 411 | register "property_list[0].name" = ""realtek,jd-src"" |
| 412 | register "property_list[0].integer" = "1" |
| 413 | device i2c 1a on end |
| 414 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 415 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 416 | device ref emmc on end |
| 417 | device ref pcie_rp7 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 418 | # RTL8111H Ethernet NIC |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 419 | chip drivers/net |
| 420 | register "customized_leds" = "0x05af" |
| 421 | register "wake" = "GPE0_DW1_07" # GPP_C7 |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 422 | register "device_index" = "0" |
Alexis Savery | 8ba64cd | 2023-08-30 20:11:34 +0000 | [diff] [blame] | 423 | register "enable_aspm_l1_2" = "1" |
Matt DeVillier | f03b8fc | 2023-11-19 16:12:56 -0600 | [diff] [blame] | 424 | device pci 00.0 on end |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 425 | end |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 426 | register "PcieRpSlotImplemented[6]" = "1" |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 427 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 428 | device ref pcie_rp11 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 429 | # X2 NVMe |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 430 | register "PcieRpSlotImplemented[10]" = "1" |
| 431 | end |
Edward O'Callaghan | 394b5fa | 2020-06-23 15:53:54 +1000 | [diff] [blame] | 432 | end |
| 433 | |
| 434 | # VR Settings Configuration for 4 Domains |
| 435 | #+----------------+-------+-------+-------+-------+ |
| 436 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 437 | #+----------------+-------+-------+-------+-------+ |
| 438 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 439 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 440 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 441 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 442 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 443 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 444 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 445 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 446 | #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 447 | #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 448 | #+----------------+-------+-------+-------+-------+ |
| 449 | #Note: IccMax settings are moved to SoC code |
| 450 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 451 | .vr_config_enable = 1, |
| 452 | .psi1threshold = VR_CFG_AMP(20), |
| 453 | .psi2threshold = VR_CFG_AMP(5), |
| 454 | .psi3threshold = VR_CFG_AMP(1), |
| 455 | .psi3enable = 1, |
| 456 | .psi4enable = 1, |
| 457 | .imon_slope = 0x0, |
| 458 | .imon_offset = 0x0, |
| 459 | .icc_max = 0, |
| 460 | .voltage_limit = 1520, |
| 461 | .ac_loadline = 1004, |
| 462 | .dc_loadline = 1004, |
| 463 | }" |
| 464 | |
| 465 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 466 | .vr_config_enable = 1, |
| 467 | .psi1threshold = VR_CFG_AMP(20), |
| 468 | .psi2threshold = VR_CFG_AMP(5), |
| 469 | .psi3threshold = VR_CFG_AMP(1), |
| 470 | .psi3enable = 1, |
| 471 | .psi4enable = 1, |
| 472 | .imon_slope = 0x0, |
| 473 | .imon_offset = 0x0, |
| 474 | .icc_max = 0, |
| 475 | .voltage_limit = 1520, |
| 476 | .ac_loadline = 181, |
| 477 | .dc_loadline = 181, |
| 478 | }" |
| 479 | |
| 480 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 481 | .vr_config_enable = 1, |
| 482 | .psi1threshold = VR_CFG_AMP(20), |
| 483 | .psi2threshold = VR_CFG_AMP(5), |
| 484 | .psi3threshold = VR_CFG_AMP(1), |
| 485 | .psi3enable = 1, |
| 486 | .psi4enable = 1, |
| 487 | .imon_slope = 0x0, |
| 488 | .imon_offset = 0x0, |
| 489 | .icc_max = 0, |
| 490 | .voltage_limit = 1520, |
| 491 | .ac_loadline = 319, |
| 492 | .dc_loadline = 319, |
| 493 | }" |
| 494 | |
| 495 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 496 | .vr_config_enable = 1, |
| 497 | .psi1threshold = VR_CFG_AMP(20), |
| 498 | .psi2threshold = VR_CFG_AMP(5), |
| 499 | .psi3threshold = VR_CFG_AMP(1), |
| 500 | .psi3enable = 1, |
| 501 | .psi4enable = 1, |
| 502 | .imon_slope = 0x0, |
| 503 | .imon_offset = 0x0, |
| 504 | .icc_max = 0, |
| 505 | .voltage_limit = 1520, |
| 506 | .ac_loadline = 319, |
| 507 | .dc_loadline = 319, |
| 508 | }" |
| 509 | |
| 510 | end |