Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* TODO: Check if this is still correct */ |
| 4 | |
| 5 | /* ACPI - create the Fixed ACPI Description Tables (FADT) */ |
| 6 | |
| 7 | #include <acpi/acpi.h> |
| 8 | #include <acpi/acpigen.h> |
| 9 | #include <amdblocks/acpi.h> |
| 10 | #include <amdblocks/cpu.h> |
| 11 | #include <amdblocks/acpimmio.h> |
| 12 | #include <amdblocks/ioapic.h> |
| 13 | #include <arch/ioapic.h> |
| 14 | #include <arch/smp/mpspec.h> |
| 15 | #include <console/console.h> |
| 16 | #include <cpu/amd/cpuid.h> |
| 17 | #include <cpu/amd/msr.h> |
| 18 | #include <cpu/x86/smm.h> |
| 19 | #include <soc/acpi.h> |
| 20 | #include <soc/iomap.h> |
| 21 | #include <soc/msr.h> |
| 22 | #include <types.h> |
| 23 | #include "chip.h" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 24 | |
| 25 | unsigned long acpi_fill_madt(unsigned long current) |
| 26 | { |
| 27 | /* create all subtables for processors */ |
| 28 | current = acpi_create_madt_lapics(current); |
| 29 | |
| 30 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 31 | FCH_IOAPIC_ID, IO_APIC_ADDR, 0); |
| 32 | |
| 33 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 34 | GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); |
| 35 | |
| 36 | /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ |
| 37 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, |
| 38 | MP_BUS_ISA, 0, 2, |
| 39 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); |
| 40 | /* SCI IRQ type override */ |
| 41 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, |
| 42 | MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, |
| 43 | MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); |
| 44 | current = acpi_fill_madt_irqoverride(current); |
| 45 | |
| 46 | /* create all subtables for processors */ |
| 47 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 48 | ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, |
| 49 | MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, |
| 50 | 1 /* 1: LINT1 connect to NMI */); |
| 51 | |
| 52 | return current; |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 57 | * in the ACPI 3.0b specification. |
| 58 | */ |
| 59 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 60 | { |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame^] | 61 | const struct soc_amd_mendocino_config *cfg = config_of_soc(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 62 | |
| 63 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); |
| 64 | |
| 65 | fadt->sci_int = ACPI_SCI_IRQ; |
| 66 | |
| 67 | if (permanent_smi_handler()) { |
| 68 | fadt->smi_cmd = APM_CNT; |
| 69 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 70 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 71 | } |
| 72 | |
| 73 | fadt->pstate_cnt = 0; |
| 74 | |
| 75 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
| 76 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
| 77 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 78 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
| 79 | |
| 80 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 81 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
| 82 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 83 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
| 84 | |
| 85 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 86 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 87 | fadt->duty_offset = 0; /* Not supported */ |
| 88 | fadt->duty_width = 0; /* Not supported */ |
| 89 | fadt->day_alrm = RTC_DATE_ALARM; |
| 90 | fadt->mon_alrm = 0; |
| 91 | fadt->century = RTC_ALT_CENTURY; |
| 92 | fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ |
| 93 | fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ |
| 94 | ACPI_FADT_C1_SUPPORTED | |
| 95 | ACPI_FADT_S4_RTC_WAKE | |
| 96 | ACPI_FADT_32BIT_TIMER | |
| 97 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 98 | ACPI_FADT_PLATFORM_CLOCK | |
| 99 | ACPI_FADT_S4_RTC_VALID | |
| 100 | ACPI_FADT_REMOTE_POWER_ON; |
| 101 | if (cfg->s0ix_enable) |
| 102 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
| 103 | |
| 104 | fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ |
| 105 | |
| 106 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 107 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 108 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 109 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 110 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 111 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 112 | |
| 113 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 114 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 115 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 116 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 117 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 118 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 119 | |
| 120 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 121 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 122 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 123 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 124 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 125 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 126 | |
| 127 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 128 | fadt->x_gpe0_blk.bit_width = 64; |
| 129 | fadt->x_gpe0_blk.bit_offset = 0; |
| 130 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 131 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 132 | fadt->x_gpe0_blk.addrh = 0x0; |
| 133 | } |
| 134 | |
| 135 | static uint32_t get_pstate_core_freq(msr_t pstate_def) |
| 136 | { |
| 137 | uint32_t core_freq, core_freq_mul, core_freq_div; |
| 138 | bool valid_freq_divisor; |
| 139 | |
| 140 | /* Core frequency multiplier */ |
| 141 | core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; |
| 142 | |
| 143 | /* Core frequency divisor ID */ |
| 144 | core_freq_div = |
| 145 | (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; |
| 146 | |
| 147 | if (core_freq_div == 0) { |
| 148 | return 0; |
| 149 | } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN) |
| 150 | && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) { |
| 151 | /* Allow 1/8 integer steps for this range */ |
| 152 | valid_freq_divisor = 1; |
| 153 | } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX) |
| 154 | && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { |
| 155 | /* Only allow 1/4 integer steps for this range */ |
| 156 | valid_freq_divisor = 1; |
| 157 | } else { |
| 158 | valid_freq_divisor = 0; |
| 159 | } |
| 160 | |
| 161 | if (valid_freq_divisor) { |
| 162 | /* 25 * core_freq_mul / (core_freq_div / 8) */ |
| 163 | core_freq = |
| 164 | ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); |
| 165 | } else { |
| 166 | printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", |
| 167 | core_freq_div); |
| 168 | core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul); |
| 169 | } |
| 170 | return core_freq; |
| 171 | } |
| 172 | |
| 173 | static uint32_t get_pstate_core_power(msr_t pstate_def) |
| 174 | { |
| 175 | uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; |
| 176 | |
| 177 | /* Core voltage ID */ |
| 178 | core_vid = |
| 179 | (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; |
| 180 | |
| 181 | /* Current value in amps */ |
| 182 | current_value_amps = |
| 183 | (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; |
| 184 | |
| 185 | /* Current divisor */ |
| 186 | current_divisor = |
| 187 | (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; |
| 188 | |
| 189 | /* Voltage */ |
Fred Reitberger | 8d2bfbc | 2022-06-07 11:34:28 -0400 | [diff] [blame] | 190 | if (core_vid == 0x00) { |
| 191 | /* Voltage off for VID code 0x00 */ |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 192 | voltage_in_uvolts = 0; |
| 193 | } else { |
| 194 | voltage_in_uvolts = |
Fred Reitberger | 8d2bfbc | 2022-06-07 11:34:28 -0400 | [diff] [blame] | 195 | SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /* Power in mW */ |
| 199 | power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps; |
| 200 | |
| 201 | switch (current_divisor) { |
| 202 | case 0: |
| 203 | break; |
| 204 | case 1: |
| 205 | power_in_mw = power_in_mw / 10L; |
| 206 | break; |
| 207 | case 2: |
| 208 | power_in_mw = power_in_mw / 100L; |
| 209 | break; |
| 210 | case 3: |
| 211 | /* current_divisor is set to an undefined value.*/ |
| 212 | printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n"); |
| 213 | power_in_mw = 0; |
| 214 | break; |
| 215 | } |
| 216 | |
| 217 | return power_in_mw; |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Populate structure describing enabled p-states and return count of enabled p-states. |
| 222 | */ |
| 223 | static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, |
| 224 | struct acpi_xpss_sw_pstate *pstate_xpss_values) |
| 225 | { |
| 226 | msr_t pstate_def; |
| 227 | size_t pstate_count, pstate; |
| 228 | uint32_t pstate_enable, max_pstate; |
| 229 | |
| 230 | pstate_count = 0; |
| 231 | max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; |
| 232 | |
| 233 | for (pstate = 0; pstate <= max_pstate; pstate++) { |
| 234 | pstate_def = rdmsr(PSTATE_0_MSR + pstate); |
| 235 | |
| 236 | pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) |
| 237 | >> PSTATE_DEF_HI_ENABLE_SHIFT; |
| 238 | if (!pstate_enable) |
| 239 | continue; |
| 240 | |
| 241 | pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); |
| 242 | pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); |
| 243 | pstate_values[pstate_count].transition_latency = 0; |
| 244 | pstate_values[pstate_count].bus_master_latency = 0; |
| 245 | pstate_values[pstate_count].control_value = pstate; |
| 246 | pstate_values[pstate_count].status_value = pstate; |
| 247 | |
| 248 | pstate_xpss_values[pstate_count].core_freq = |
| 249 | (uint64_t)pstate_values[pstate_count].core_freq; |
| 250 | pstate_xpss_values[pstate_count].power = |
| 251 | (uint64_t)pstate_values[pstate_count].power; |
| 252 | pstate_xpss_values[pstate_count].transition_latency = 0; |
| 253 | pstate_xpss_values[pstate_count].bus_master_latency = 0; |
| 254 | pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; |
| 255 | pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; |
| 256 | pstate_count++; |
| 257 | } |
| 258 | |
| 259 | return pstate_count; |
| 260 | } |
| 261 | |
| 262 | void generate_cpu_entries(const struct device *device) |
| 263 | { |
| 264 | int logical_cores; |
| 265 | size_t pstate_count, cpu, proc_blk_len; |
| 266 | struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; |
| 267 | struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; |
| 268 | uint32_t threads_per_core, proc_blk_addr; |
| 269 | uint32_t cstate_base_address = |
| 270 | rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK; |
| 271 | |
| 272 | const acpi_addr_t perf_ctrl = { |
| 273 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 274 | .bit_width = 64, |
| 275 | .addrl = PS_CTL_REG, |
| 276 | }; |
| 277 | const acpi_addr_t perf_sts = { |
| 278 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 279 | .bit_width = 64, |
| 280 | .addrl = PS_STS_REG, |
| 281 | }; |
| 282 | |
| 283 | const acpi_cstate_t cstate_info[] = { |
| 284 | [0] = { |
| 285 | .ctype = 1, |
| 286 | .latency = 1, |
| 287 | .power = 0, |
| 288 | .resource = { |
| 289 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 290 | .bit_width = 2, |
| 291 | .bit_offset = 2, |
| 292 | .addrl = 0, |
| 293 | .addrh = 0, |
| 294 | }, |
| 295 | }, |
| 296 | [1] = { |
| 297 | .ctype = 2, |
| 298 | .latency = 0x12, |
| 299 | .power = 0, |
| 300 | .resource = { |
| 301 | .space_id = ACPI_ADDRESS_SPACE_IO, |
| 302 | .bit_width = 8, |
| 303 | .bit_offset = 0, |
| 304 | .addrl = cstate_base_address + 1, |
| 305 | .addrh = 0, |
| 306 | .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, |
| 307 | }, |
| 308 | }, |
| 309 | [2] = { |
| 310 | .ctype = 3, |
| 311 | .latency = 350, |
| 312 | .power = 0, |
| 313 | .resource = { |
| 314 | .space_id = ACPI_ADDRESS_SPACE_IO, |
| 315 | .bit_width = 8, |
| 316 | .bit_offset = 0, |
| 317 | .addrl = cstate_base_address + 2, |
| 318 | .addrh = 0, |
| 319 | .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, |
| 320 | }, |
| 321 | }, |
| 322 | }; |
| 323 | |
Felix Held | d4b5ad0 | 2022-01-25 04:14:05 +0100 | [diff] [blame] | 324 | threads_per_core = get_threads_per_core(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 325 | pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); |
| 326 | logical_cores = get_cpu_count(); |
| 327 | |
| 328 | for (cpu = 0; cpu < logical_cores; cpu++) { |
| 329 | |
| 330 | if (cpu == 0) { |
| 331 | /* BSP values for \_SB.Pxxx */ |
| 332 | proc_blk_len = 6; |
| 333 | proc_blk_addr = ACPI_GPE0_BLK; |
| 334 | } else { |
| 335 | /* AP values for \_SB.Pxxx */ |
| 336 | proc_blk_addr = 0; |
| 337 | proc_blk_len = 0; |
| 338 | } |
| 339 | |
| 340 | acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len); |
| 341 | |
| 342 | acpigen_write_pct_package(&perf_ctrl, &perf_sts); |
| 343 | |
| 344 | acpigen_write_pss_object(pstate_values, pstate_count); |
| 345 | |
| 346 | acpigen_write_xpss_object(pstate_xpss_values, pstate_count); |
| 347 | |
| 348 | if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) |
| 349 | acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, |
| 350 | HW_ALL); |
| 351 | else |
| 352 | acpigen_write_PSD_package(0, logical_cores, SW_ALL); |
| 353 | |
| 354 | acpigen_write_PPC(0); |
| 355 | |
| 356 | acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); |
| 357 | |
| 358 | acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, |
| 359 | CSD_HW_ALL, 0); |
| 360 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 361 | acpigen_pop_len(); |
| 362 | } |
| 363 | |
| 364 | acpigen_write_processor_package("PPKG", 0, logical_cores); |
| 365 | } |