| Michael Büchler | 4f1378e | 2020-09-06 19:59:18 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <stdint.h> |
| 4 | |
| 5 | #include <bootblock_common.h> |
| 6 | #include <device/pci_ops.h> |
| 7 | #include <device/pnp_ops.h> |
| 8 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 9 | #include <option.h> |
| 10 | #include <southbridge/intel/bd82x6x/pch.h> |
| 11 | #include <superio/nuvoton/common/nuvoton.h> |
| 12 | #include <superio/nuvoton/nct6776/nct6776.h> |
| 13 | |
| 14 | #define GLOBAL_DEV PNP_DEV(0x2e, 0) |
| 15 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) |
| 16 | #define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V) |
| 17 | |
| 18 | /* As defined in cmos.layout */ |
| 19 | enum cpu_fan_tach_src { |
| 20 | CPU_FAN_HEADER_NONE, |
| 21 | CPU_FAN_HEADER_1, |
| 22 | CPU_FAN_HEADER_2, |
| 23 | CPU_FAN_HEADER_BOTH |
| 24 | }; |
| 25 | |
| 26 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 27 | { 1, 0, 0 }, |
| 28 | { 1, 0, 0 }, |
| 29 | { 1, 1, 1 }, |
| 30 | { 1, 1, 1 }, |
| 31 | { 1, 1, 2 }, |
| 32 | { 1, 1, 2 }, |
| 33 | { 1, 0, 3 }, |
| 34 | { 1, 0, 3 }, |
| 35 | { 1, 0, 4 }, |
| 36 | { 1, 0, 4 }, |
| 37 | { 1, 0, 6 }, |
| 38 | { 1, 1, 5 }, |
| 39 | { 1, 1, 5 }, |
| 40 | { 1, 0, 6 }, |
| 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * The tachometer signal that goes to CPUFANIN of the Super I/O is set via |
| 45 | * GPIOs. |
| 46 | * |
| 47 | * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. |
| 48 | * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. |
| 49 | * When both are '0' and both fans are connected, wrong readings will |
| 50 | * be reported. |
| 51 | */ |
| 52 | static u8 get_cpufanin_gpio_config(void) |
| 53 | { |
| 54 | switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) { |
| 55 | case CPU_FAN_HEADER_NONE: |
| 56 | return 0xff; |
| 57 | case CPU_FAN_HEADER_1: |
| 58 | default: |
| 59 | return 0x7f; |
| 60 | case CPU_FAN_HEADER_2: |
| 61 | return 0xbf; |
| 62 | case CPU_FAN_HEADER_BOTH: |
| 63 | return 0x3f; |
| 64 | } |
| 65 | }; |
| 66 | |
| 67 | void bootblock_mainboard_early_init(void) |
| 68 | { |
| 69 | nuvoton_pnp_enter_conf_state(GLOBAL_DEV); |
| 70 | |
| 71 | /* Configure Super I/O pins */ |
| 72 | pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); |
| 73 | pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); |
| 74 | pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); |
| 75 | pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); |
| 76 | pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); |
| 77 | pnp_write_config(GLOBAL_DEV, 0x2b, 0x08); |
| 78 | pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); |
| 79 | |
| 80 | /* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */ |
| 81 | pnp_set_logical_device(GPIO6789_DEV); |
| 82 | pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); |
| 83 | pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config()); |
| 84 | |
| 85 | nuvoton_pnp_exit_conf_state(GLOBAL_DEV); |
| 86 | |
| 87 | /* Enable UART */ |
| 88 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 89 | } |
| 90 | |
| 91 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 92 | { |
| 93 | read_spd(&spd[0], 0x50, id_only); |
| 94 | read_spd(&spd[1], 0x51, id_only); |
| 95 | read_spd(&spd[2], 0x52, id_only); |
| 96 | read_spd(&spd[3], 0x53, id_only); |
| 97 | } |