Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <types.h> |
| 6 | #include <soc/gpio.h> |
| 7 | #include <vendorcode/google/chromeos/chromeos.h> |
| 8 | |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 9 | /* Pad configuration in ramstage */ |
| 10 | static const struct pad_config gpio_table[] = { |
Bora Guvendik | 5e6319b | 2023-05-31 11:10:42 -0700 | [diff] [blame] | 11 | /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R */ |
| 12 | PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), |
| 13 | /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R */ |
| 14 | PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), |
| 15 | /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R */ |
| 16 | PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), |
| 17 | /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R */ |
| 18 | PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), |
| 19 | /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L */ |
| 20 | PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), |
| 21 | /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R */ |
| 22 | PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), |
| 23 | /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L */ |
| 24 | PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 25 | /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ |
| 26 | PAD_CFG_GPO(GPP_A11, 0, DEEP), |
| 27 | /* GPP_A12 : [] ==> EN_UCAM_PWR */ |
| 28 | PAD_CFG_GPO(GPP_A12, 0, DEEP), |
| 29 | /* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */ |
| 30 | PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG), |
| 31 | /* GPP_A14 : net NC is not present in the given design */ |
| 32 | PAD_NC(GPP_A14, NONE), |
| 33 | /* GPP_A15 : net NC is not present in the given design */ |
| 34 | PAD_NC(GPP_A15, NONE), |
Bora Guvendik | 5e6319b | 2023-05-31 11:10:42 -0700 | [diff] [blame] | 35 | /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */ |
| 36 | PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 37 | /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ |
| 38 | PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 39 | |
| 40 | /* GPP_A18 : net NC. Test pad. */ |
| 41 | PAD_NC(GPP_A18, NONE), |
| 42 | /* GPP_A19 : [] ==> EN_PP3300_SSD */ |
| 43 | PAD_CFG_GPO(GPP_A19, 1, DEEP), |
| 44 | /* GPP_A20 : [] ==> SSD_PERST_L */ |
| 45 | PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), |
| 46 | /* GPP_A21 : [] ==> PMCALERT */ |
| 47 | PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), |
| 48 | |
| 49 | /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */ |
| 50 | PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 51 | /* GPP_B01 : [] ==> BT_DISABLE_L */ |
| 52 | PAD_CFG_GPO(GPP_B01, 1, DEEP), |
| 53 | /* GPP_B02 : net NC is not present in the given design */ |
| 54 | PAD_NC(GPP_B02, NONE), |
| 55 | /* GPP_B03 : net NC is not present in the given design */ |
| 56 | PAD_NC(GPP_B03, NONE), |
| 57 | /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ |
| 58 | PAD_NC(GPP_B04, NONE), |
| 59 | /* GPP_B05 : [] ==> SPKR_INT_L_R */ |
| 60 | /* GPP_B05 : net NC is not present in the given design */ |
| 61 | PAD_NC(GPP_B05, NONE), |
| 62 | /* GPP_B06 : [] ==> HP_INT_L_R */ |
| 63 | PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), |
| 64 | /* GPP_B07 : [] ==> EN_SPKR */ |
| 65 | PAD_CFG_GPO(GPP_B07, 1, DEEP), |
| 66 | /* GPP_B08 : [] ==> EN_FP_PWR */ |
| 67 | PAD_CFG_GPO_LOCK(GPP_B08, 1, LOCK_CONFIG), |
| 68 | /* GPP_B09 : net NC is not present in the given design */ |
| 69 | PAD_NC(GPP_B09, NONE), |
| 70 | /* GPP_B10 : net NC is not present in the given design */ |
| 71 | PAD_NC(GPP_B10, NONE), |
| 72 | /* GPP_B11 : [] ==> USB_C1_OC_ODL*/ |
| 73 | PAD_CFG_NF_LOCK(GPP_B11, NONE, NF1, LOCK_CONFIG), |
| 74 | /* GPP_B12 : [] ==> SLP_SO_R_L */ |
| 75 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 76 | /* GPP_B13 : [] ==> PLT_RST_L */ |
| 77 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 78 | /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ |
| 79 | PAD_NC(GPP_B14, NONE), |
| 80 | /* GPP_B15 : [] ==> USB_OC3# */ |
| 81 | PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), |
| 82 | /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ |
| 83 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), |
| 84 | /* GPP_B17 : net NC. Test pad. */ |
| 85 | PAD_NC(GPP_B17, NONE), |
| 86 | /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ |
| 87 | PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), |
| 88 | /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ |
| 89 | PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), |
| 90 | /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ |
| 91 | PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), |
| 92 | /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ |
| 93 | PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), |
| 94 | /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ |
| 95 | PAD_CFG_GPO(GPP_B22, 0, DEEP), |
| 96 | /* GPP_B23 : net NC. Test pad. */ |
| 97 | PAD_NC(GPP_B23, NONE), |
| 98 | /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ |
| 99 | PAD_CFG_GPO(GPP_C00, 0, DEEP), |
| 100 | /* GPP_C01 : [] ==> SOC_TCHSCR_RST_L */ |
| 101 | PAD_CFG_GPO(GPP_C01, 0, DEEP), |
| 102 | /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ |
| 103 | PAD_NC(GPP_C02, NONE), |
| 104 | /* GPP_C03 : [] ==> SOC_TCP_SMBUS_CLK*/ |
Simon Zhou | 4eee506 | 2023-06-02 13:06:06 +0800 | [diff] [blame^] | 105 | PAD_NC(GPP_C03, NONE), |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 106 | /* GPP_C04 : [] ==> SOC_TCP_SMBUS_SDA*/ |
Simon Zhou | 4eee506 | 2023-06-02 13:06:06 +0800 | [diff] [blame^] | 107 | PAD_NC(GPP_C04, NONE), |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 108 | /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ |
| 109 | PAD_NC(GPP_C05, NONE), |
| 110 | /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ |
| 111 | PAD_CFG_GPO(GPP_C06, 1, DEEP), |
| 112 | /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ |
| 113 | PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), |
| 114 | /* GPP_C08 : [] ==> SOCHOT_ODL */ |
| 115 | PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), |
| 116 | /* GPP_C09 : net NC is not present in the given design */ |
| 117 | PAD_NC(GPP_C09, NONE), |
| 118 | /* GPP_C10 : net NC is not present in the given design */ |
| 119 | PAD_NC(GPP_C10, NONE), |
| 120 | /* GPP_C11 : [] ==> SD_CLKREQ_ODL */ |
| 121 | /* PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),*/ |
| 122 | PAD_NC(GPP_C11, NONE), |
| 123 | /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ |
| 124 | /* PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),*/ |
| 125 | PAD_NC(GPP_C12, NONE), |
| 126 | /* GPP_C13 : [] ==> SSD_CLKREQ_ODL */ |
| 127 | PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), |
| 128 | /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ |
| 129 | PAD_CFG_GPO(GPP_C15, 1, DEEP), |
| 130 | /* GPP_C16 : [] ==> USB_C0_AUX_DC_P */ |
| 131 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF6), |
| 132 | /* GPP_C17 : [] ==> USB_C0_AUX_DC_N */ |
| 133 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF6), |
| 134 | /* GPP_C18 : [] ==> USB_C0_LSX_TX */ |
| 135 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 136 | /* GPP_C19 : [] ==> USB_C0_LSX_RX */ |
| 137 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 138 | /* GPP_C20 : [] ==> SOC_FP_BOOT0 */ |
| 139 | PAD_CFG_GPO_LOCK(GPP_C20, 0, LOCK_CONFIG), |
| 140 | /* GPP_C21 : [] ==> FP_RST_ODL */ |
| 141 | PAD_CFG_GPO_LOCK(GPP_C21, 1, LOCK_CONFIG), |
| 142 | /* GPP_C22 : [] ==> USB_C1_LSX_TX */ |
| 143 | PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), |
| 144 | /* GPP_C23 : [] ==> USB_C1_LSX_RX */ |
| 145 | PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), |
| 146 | |
| 147 | /* GPP_D00 : net NC is not present in the given design */ |
| 148 | PAD_NC(GPP_D00, NONE), |
| 149 | /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */ |
| 150 | PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG), |
| 151 | /* GPP_D02 : [] ==> SD_PERST_L */ |
| 152 | PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), |
| 153 | /* GPP_D03 : [] ==> EN_PP3300_SD */ |
| 154 | PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), |
| 155 | /* GPP_D04 : net NC is not present in the given design */ |
| 156 | PAD_NC(GPP_D04, NONE), |
| 157 | /* GPP_D05 : [] ==> UART0_RXD. */ |
| 158 | PAD_CFG_NF_LOCK(GPP_D05, NONE, NF1, LOCK_CONFIG), |
| 159 | /* GPP_D06 : [] ==> UART0_TXD. */ |
| 160 | PAD_CFG_NF_LOCK(GPP_D06, NONE, NF1, LOCK_CONFIG), |
| 161 | /* GPP_D07 : net NC. Test pad. */ |
| 162 | PAD_NC(GPP_D07, NONE), |
| 163 | /* GPP_D08 : net NC. Test pad. */ |
| 164 | PAD_NC(GPP_D08, NONE), |
| 165 | /* GPP_D09 : [] ==> I2S_MCLK_R */ |
| 166 | PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), |
| 167 | /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ |
| 168 | PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), |
| 169 | /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ |
| 170 | PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), |
| 171 | /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ |
| 172 | PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), |
| 173 | /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ |
| 174 | /* GPP_D13 : net NC is not present in the given design */ |
| 175 | PAD_NC(GPP_D13, NONE), |
| 176 | /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ |
| 177 | PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), |
| 178 | /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ |
| 179 | PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), |
| 180 | /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ |
| 181 | PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), |
| 182 | /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ |
| 183 | PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), |
| 184 | /* GPP_D18 : net NC is not present in the given design */ |
| 185 | PAD_NC(GPP_D18, NONE), |
| 186 | /* GPP_D19 : [] ==> SD_CLKREQ_ODL */ |
| 187 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 188 | /* GPP_D20 : net NC is not present in the given design */ |
| 189 | PAD_NC(GPP_D20, NONE), |
| 190 | /* GPP_D21 : net NC is not present in the given design */ |
| 191 | PAD_NC(GPP_D21, NONE), |
| 192 | /* GPP_D22 : net NC. Test pad. */ |
| 193 | PAD_NC(GPP_D22, NONE), |
| 194 | /* GPP_D23 : net NC. Test pad. */ |
| 195 | PAD_NC(GPP_D23, NONE), |
| 196 | |
| 197 | /* GPP_E00 : net NC is not present in the given design */ |
| 198 | PAD_NC(GPP_E00, NONE), |
| 199 | /* GPP_E01 : MEM_STRAP_2 ==> Component NC */ |
| 200 | PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), |
| 201 | /* GPP_E02 : MEM_STRAP_1 ==> Component NC */ |
| 202 | PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), |
| 203 | /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ |
| 204 | PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 205 | /* GPP_E04 : net NC is not present in the given design */ |
| 206 | PAD_NC(GPP_E04, NONE), |
| 207 | /* GPP_E05 : net NC is not present in the given design */ |
| 208 | PAD_NC(GPP_E05, NONE), |
| 209 | /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ |
| 210 | PAD_NC(GPP_E06, NONE), |
| 211 | /* GPP_E07 : net NC is not present in the given design */ |
| 212 | PAD_NC(GPP_E07, NONE), |
| 213 | /* GPP_E08 : net NC is not present in the given design */ |
| 214 | PAD_NC(GPP_E08, NONE), |
| 215 | /* GPP_E09 : No heuristic was found useful */ |
| 216 | PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), |
| 217 | /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ |
| 218 | PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E10, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 219 | /* GPP_E11 : [] ==> MEM_STRAP_0 */ |
| 220 | PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), |
| 221 | /* GPP_E12 : [] ==> MEM_STRAP_3 */ |
| 222 | PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), |
| 223 | /* GPP_E13 : [] ==> MEM_CH_SEL */ |
| 224 | PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), |
| 225 | /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ |
| 226 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 227 | /* GPP_E15 : net NC is not present in the given design */ |
| 228 | PAD_NC(GPP_E15, NONE), |
| 229 | /* GPP_E16 : net NC. Test pad. */ |
| 230 | PAD_NC(GPP_E16, NONE), |
| 231 | /* GPP_E17 : net NC. Test pad. */ |
| 232 | PAD_NC(GPP_E17, NONE), |
| 233 | /* GPP_E22 : [] ==> WIFI_DISABLE_L */ |
| 234 | PAD_CFG_GPO(GPP_E22, 1, DEEP), |
| 235 | |
| 236 | /* GPP_F00 : [] ==> CNV_BRI_DT_R */ |
| 237 | PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), |
| 238 | /* GPP_F01 : [] ==> CNV_BRI_RSP */ |
| 239 | PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), |
| 240 | /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ |
| 241 | PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), |
| 242 | /* GPP_F03 : [] ==> CNV_RGI_RSP */ |
| 243 | PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), |
| 244 | /* GPP_F04 : [] ==> CNV_RF_RST_L */ |
| 245 | PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), |
| 246 | /* GPP_F05 : [] ==> CNV_CLKREQ */ |
| 247 | PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), |
| 248 | /* GPP_F06 : net NC is not present in the given design */ |
| 249 | PAD_NC(GPP_F06, NONE), |
| 250 | /* GPP_F07 : [] ==> UCAM_MCLK_R */ |
| 251 | PAD_CFG_NF(GPP_F07, NONE, DEEP, NF1), |
| 252 | /* GPP_F08 : net NC is not present in the given design */ |
| 253 | PAD_NC(GPP_F08, NONE), |
| 254 | /* GPP_F09 : net NC is not present in the given design */ |
| 255 | PAD_NC(GPP_F09, NONE), |
| 256 | /* GPP_F10 : net NC is not present in the given design */ |
| 257 | PAD_NC(GPP_F10, NONE), |
| 258 | /* GPP_F11 : GSP1_SOC_CLK_R */ |
| 259 | PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5), |
| 260 | /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */ |
| 261 | PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), |
| 262 | /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */ |
| 263 | PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), |
| 264 | /* GPP_F14 : net NC. Test pad. */ |
| 265 | PAD_NC(GPP_F14, NONE), |
| 266 | /* GPP_F15 : net NC. Test pad. */ |
| 267 | PAD_NC(GPP_F15, NONE), |
| 268 | /* GPP_F16 : net NC. Test pad. */ |
| 269 | PAD_NC(GPP_F16, NONE), |
| 270 | /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ |
| 271 | PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), |
| 272 | /* GPP_F18 : net NC is not present in the given design */ |
| 273 | PAD_NC(GPP_F18, NONE), |
| 274 | /* GPP_F19 : [] ==> GPP_F19_STRAP */ |
| 275 | PAD_NC(GPP_F19, NONE), |
| 276 | /* GPP_F20 : [] ==> GPP_F20_STRAP */ |
| 277 | PAD_NC(GPP_F20, NONE), |
| 278 | /* GPP_F21 : [] ==> GPP_F21_STRAP */ |
| 279 | PAD_NC(GPP_F21, NONE), |
| 280 | /* GPP_F22 : net NC is not present in the given design */ |
| 281 | PAD_NC(GPP_F22, NONE), |
| 282 | /* GPP_F23 : net NC is not present in the given design */ |
| 283 | PAD_NC(GPP_F23, NONE), |
| 284 | |
| 285 | /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ |
| 286 | PAD_NC(GPP_H00, NONE), |
| 287 | /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ |
| 288 | PAD_NC(GPP_H01, NONE), |
| 289 | /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ |
| 290 | PAD_NC(GPP_H02, NONE), |
| 291 | /* GPP_H04 : net NC is not present in the given design */ |
| 292 | PAD_NC(GPP_H04, NONE), |
| 293 | /* GPP_H05 : net NC is not present in the given design */ |
| 294 | PAD_NC(GPP_H05, NONE), |
| 295 | /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ |
| 296 | PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), |
| 297 | /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ |
| 298 | PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), |
| 299 | /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ |
| 300 | PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), |
| 301 | /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ |
| 302 | PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), |
| 303 | /* GPP_H10 : [] ==> SOC_WP_OD */ |
| 304 | PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), |
| 305 | /* GPP_H11 : net NC is not present in the given design */ |
| 306 | PAD_NC(GPP_H11, NONE), |
| 307 | /* GPP_H13 : [] ==> CPU_C10_GATE_L */ |
| 308 | PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), |
| 309 | /* GPP_H14 : [] ==> SLP_S0_GATE_R */ |
| 310 | PAD_CFG_GPO(GPP_H14, 1, PLTRST), |
| 311 | /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ |
| 312 | /* GPP_H15 : net NC is not present in the given design */ |
| 313 | PAD_NC(GPP_H15, NONE), |
| 314 | /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ |
| 315 | PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), |
| 316 | /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ |
| 317 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 318 | /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ |
| 319 | PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), |
| 320 | /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ |
| 321 | PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), |
| 322 | /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ |
| 323 | PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), |
| 324 | /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ |
| 325 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 326 | |
| 327 | /* GPP_S00 : net NC is not present in the given design */ |
| 328 | PAD_NC(GPP_S00, NONE), |
| 329 | /* GPP_S01 : net NC is not present in the given design */ |
| 330 | PAD_NC(GPP_S01, NONE), |
| 331 | /* GPP_S02 : net NC is not present in the given design */ |
| 332 | PAD_NC(GPP_S02, NONE), |
| 333 | /* GPP_S03 : net NC is not present in the given design */ |
| 334 | PAD_NC(GPP_S03, NONE), |
| 335 | /* GPP_S04 : net NC is not present in the given design */ |
| 336 | PAD_NC(GPP_S04, NONE), |
| 337 | /* GPP_S05 : net NC is not present in the given design */ |
| 338 | PAD_NC(GPP_S05, NONE), |
| 339 | /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ |
| 340 | PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), |
| 341 | /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ |
| 342 | PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), |
| 343 | |
| 344 | /* GPP_V00 : [] ==> BATLOW_L */ |
| 345 | PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), |
| 346 | /* GPP_V01 : [] ==> ACPRESENT */ |
| 347 | PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), |
| 348 | /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ |
| 349 | PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), |
| 350 | /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ |
| 351 | PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), |
| 352 | /* GPP_V04 : [] ==> SLP_S3_L */ |
| 353 | PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), |
| 354 | /* GPP_V05 : [] ==> SLP_S4_L */ |
| 355 | PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), |
| 356 | /* GPP_V06 : [] ==> SOC_SLP_A_L */ |
| 357 | PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), |
| 358 | /* GPP_V08 : [] ==> SOC_SUSCLK */ |
| 359 | PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), |
| 360 | /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ |
| 361 | PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), |
| 362 | /* GPP_V10 : [] ==> SLP_S5_L */ |
| 363 | PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), |
| 364 | /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/ |
| 365 | PAD_NC(GPP_V11, NONE), |
| 366 | /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ |
| 367 | PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), |
| 368 | /* GPP_V14 : [] ==> SOC_WAKE_L */ |
| 369 | PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), |
| 370 | /* GPP_V22 : [] ==> WCAM_RST_L */ |
| 371 | /* GPP_V22 : net NC is not present in the given design */ |
| 372 | PAD_NC(GPP_V22, NONE), |
| 373 | /* GPP_V23 : [] ==> UCAM_RST_L */ |
| 374 | PAD_CFG_GPO(GPP_V23, 0, DEEP), |
| 375 | }; |
| 376 | |
| 377 | /* Early pad configuration in bootblock */ |
| 378 | static const struct pad_config early_gpio_table[] = { |
| 379 | /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ |
| 380 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), |
| 381 | /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ |
| 382 | PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), |
| 383 | /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ |
| 384 | PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), |
| 385 | |
| 386 | /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ |
| 387 | PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), |
| 388 | /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ |
| 389 | PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), |
| 390 | |
| 391 | /* GPP_D03 : [] ==> EN_PP3300_SD */ |
| 392 | PAD_CFG_GPO(GPP_D03, 1, DEEP), |
| 393 | |
| 394 | /* GPP_E13 : [] ==> MEM_CH_SEL */ |
| 395 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 396 | |
| 397 | /* GPP_A20 : [] ==> SSD_PERST_L */ |
| 398 | PAD_CFG_GPO(GPP_A20, 0, DEEP), |
| 399 | |
| 400 | /* GPP_H10 : [] ==> SOC_WP_OD */ |
| 401 | PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), |
| 402 | }; |
| 403 | |
| 404 | static const struct pad_config romstage_gpio_table[] = { |
| 405 | /* GPP_B11 : [] ==> EN_FP_PWR */ |
| 406 | PAD_CFG_GPO(GPP_B08, 0, DEEP), |
| 407 | /* A20 : [] ==> SSD_PERST_L */ |
| 408 | PAD_CFG_GPO(GPP_A20, 0, DEEP), |
Simon Zhou | 6477d19 | 2023-05-17 10:12:29 +0800 | [diff] [blame] | 409 | /* GPP_C21 : [] ==> FP_RST_ODL */ |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 410 | PAD_CFG_GPO(GPP_C21, 0, DEEP), |
| 411 | /* GPP_D02 : [] ==> SD_PERST_L */ |
| 412 | PAD_CFG_GPO(GPP_D02, 1, DEEP), |
| 413 | }; |
| 414 | |
Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 415 | const struct pad_config *variant_gpio_table(size_t *num) |
| 416 | { |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 417 | *num = ARRAY_SIZE(gpio_table); |
| 418 | return gpio_table; |
Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 422 | { |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 423 | *num = ARRAY_SIZE(early_gpio_table); |
| 424 | return early_gpio_table; |
Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 425 | } |
| 426 | |
| 427 | static const struct cros_gpio cros_gpios[] = { |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 428 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 429 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 430 | }; |
| 431 | |
| 432 | DECLARE_CROS_GPIOS(cros_gpios); |
| 433 | |
| 434 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 435 | { |
Kun Liu | 8ba2ecf | 2023-04-17 19:54:24 +0800 | [diff] [blame] | 436 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 437 | return romstage_gpio_table; |
Simon Zhou | 2cf25eb | 2023-04-14 14:21:00 +0800 | [diff] [blame] | 438 | } |