Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <cbmem.h> |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <delay.h> |
| 28 | #include <broadwell/adsp.h> |
| 29 | #include <broadwell/device_nvs.h> |
| 30 | #include <broadwell/iobp.h> |
| 31 | #include <broadwell/nvs.h> |
| 32 | #include <broadwell/pch.h> |
| 33 | #include <broadwell/ramstage.h> |
| 34 | #include <broadwell/rcba.h> |
| 35 | #include <chip.h> |
| 36 | |
| 37 | static void adsp_init(struct device *dev) |
| 38 | { |
| 39 | config_t *config = dev->chip_info; |
| 40 | struct resource *bar0, *bar1; |
| 41 | u32 tmp32; |
| 42 | |
| 43 | /* Ensure memory and bus master are enabled */ |
| 44 | tmp32 = pci_read_config32(dev, PCI_COMMAND); |
| 45 | tmp32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 46 | pci_write_config32(dev, PCI_COMMAND, tmp32); |
| 47 | |
| 48 | /* Find BAR0 and BAR1 */ |
| 49 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 50 | if (!bar0) |
| 51 | return; |
| 52 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 53 | if (!bar1) |
| 54 | return; |
| 55 | |
| 56 | /* |
| 57 | * Set LTR value in DSP shim LTR control register to 3ms |
| 58 | * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h |
| 59 | */ |
| 60 | tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 61 | write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0), |
| 62 | ADSP_SHIM_LTRC_VALUE); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 63 | |
| 64 | /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ |
| 65 | pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); |
| 66 | |
| 67 | /* Program ADSP IOBP VDLDAT1 to 0x040100 */ |
| 68 | pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); |
| 69 | |
| 70 | /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ |
| 71 | tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 72 | if (pch_is_wpt()) { |
| 73 | if (config->adsp_d3_pg_enable) { |
| 74 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; |
| 75 | if (config->adsp_sram_pg_enable) |
| 76 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
| 77 | else |
| 78 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 79 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 80 | tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 81 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 82 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 83 | if (config->adsp_d3_pg_enable) { |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 84 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 85 | if (config->adsp_sram_pg_enable) |
| 86 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 87 | else |
| 88 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 89 | } else { |
| 90 | tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 91 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 92 | } |
| 93 | pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); |
| 94 | |
| 95 | /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ |
| 96 | RCBA32_OR(0x3350, (1 << 10)); |
| 97 | |
| 98 | /* Set DSP IOBP PMCTL 0x1e0=0x3f */ |
| 99 | pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); |
| 100 | |
| 101 | if (config->sio_acpi_mode) { |
| 102 | /* Configure for ACPI mode */ |
| 103 | global_nvs_t *gnvs; |
| 104 | |
| 105 | printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); |
| 106 | |
| 107 | /* Find ACPI NVS to update BARs */ |
| 108 | gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 109 | if (!gnvs) { |
| 110 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 111 | return; |
| 112 | } |
| 113 | |
| 114 | /* Save BAR0 and BAR1 to ACPI NVS */ |
| 115 | gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base; |
| 116 | gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base; |
| 117 | gnvs->dev.enable[SIO_NVS_ADSP] = 1; |
| 118 | |
| 119 | /* Set PCI Config Disable Bit */ |
| 120 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); |
| 121 | |
| 122 | /* Set interrupt de-assert/assert opcode override to IRQ3 */ |
| 123 | pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); |
| 124 | |
| 125 | /* Enable IRQ3 in RCBA */ |
| 126 | RCBA32_OR(ACPIIRQEN, ADSP_ACPI_IRQEN); |
| 127 | |
| 128 | /* Set ACPI Interrupt Enable Bit */ |
| 129 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, |
| 130 | ADSP_PCICFGCTL_ACPIIE); |
| 131 | |
| 132 | /* Put ADSP in D3hot */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 133 | tmp32 = read32(res2mmio(bar1, PCH_PCS, 0)); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 134 | tmp32 |= PCH_PCS_PS_D3HOT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 135 | write32(res2mmio(bar1, PCH_PCS, 0), tmp32); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 136 | } else { |
| 137 | printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); |
| 138 | |
| 139 | /* Configure for PCI mode */ |
| 140 | pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); |
| 141 | |
| 142 | /* Clear ACPI Interrupt Enable Bit */ |
| 143 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, |
| 144 | ~(ADSP_PCICFGCTL_SPCBAD | ADSP_PCICFGCTL_ACPIIE), 0); |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | static struct device_operations adsp_ops = { |
| 149 | .read_resources = &pci_dev_read_resources, |
| 150 | .set_resources = &pci_dev_set_resources, |
| 151 | .enable_resources = &pci_dev_enable_resources, |
| 152 | .init = &adsp_init, |
| 153 | .ops_pci = &broadwell_pci_ops, |
| 154 | }; |
| 155 | |
| 156 | static const unsigned short pci_device_ids[] = { |
| 157 | 0x9c36, /* LynxPoint */ |
| 158 | 0x9cb6, /* WildcatPoint */ |
| 159 | 0 |
| 160 | }; |
| 161 | |
| 162 | static const struct pci_driver pch_adsp __pci_driver = { |
| 163 | .ops = &adsp_ops, |
| 164 | .vendor = PCI_VENDOR_ID_INTEL, |
| 165 | .devices = pci_device_ids, |
| 166 | }; |
| 167 | |