Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Southbridge Init during POWER-ON |
| 6 | * |
| 7 | * Prepare Southbridge environment during power on stage. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: CIMx-SB |
| 11 | * @e sub-project: |
| 12 | * @e \$Revision:$ @e \$Date:$ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #include "SBPLATFORM.h" |
| 48 | #include "cbtypes.h" |
| 49 | /** |
| 50 | * sbPorInitPciTable - PCI device registers initial during the power on stage. |
| 51 | */ |
Elyes HAOUAS | ad1456f | 2019-06-22 09:52:12 +0200 | [diff] [blame] | 52 | static const REG8MASK sbPorInitPciTable[] = |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 53 | { |
| 54 | // SATA device |
| 55 | {0x00, SATA_BUS_DEV_FUN, 0}, |
| 56 | {SB_SATA_REG84 + 3, ~BIT2, 0}, |
| 57 | {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5}, |
| 58 | {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5}, |
| 59 | {0xFF, 0xFF, 0xFF}, |
| 60 | // LPC Device (Bus 0, Dev 20, Func 3) |
| 61 | {0x00, LPC_BUS_DEV_FUN, 0}, |
| 62 | {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, |
| 63 | {SB_LPC_REG7C, 0x00, BIT0 + BIT2}, |
| 64 | {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, |
| 65 | // A12 set 0xBB [5:3] = 111 to improve SPI timing margin. |
| 66 | // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) |
| 67 | {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, |
| 68 | {SB_LPC_REGBA, 0x9F, BIT5 + BIT6}, |
| 69 | {0xFF, 0xFF, 0xFF}, |
| 70 | // P2P Bridge (Bus 0, Dev 20, Func 4) |
| 71 | {0x00, PCIB_BUS_DEV_FUN, 0}, |
| 72 | {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, |
| 73 | // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge. |
| 74 | {SB_PCIB_REG1C, 0x00, 0xF0}, |
| 75 | {SB_PCIB_REG1D, 0x00, 0x00}, |
| 76 | {SB_PCIB_REG04, 0x00, 0x21}, |
| 77 | {SB_PCIB_REG40, 0xDF, 0x20}, |
| 78 | {SB_PCIB_REG50, 0x02, 0x01}, |
| 79 | {0xFF, 0xFF, 0xFF}, |
| 80 | }; |
| 81 | |
| 82 | /** |
| 83 | * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. |
| 84 | */ |
Elyes HAOUAS | ad1456f | 2019-06-22 09:52:12 +0200 | [diff] [blame] | 85 | static const AcpiRegWrite sbPmioPorInitTable[] = |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 86 | { |
| 87 | {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, |
| 88 | {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, |
| 89 | {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0}, |
| 90 | {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0}, |
| 91 | {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7}, |
| 92 | {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0}, |
| 93 | {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E}, |
| 94 | {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40}, |
| 95 | {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08}, |
| 96 | {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1}, |
| 97 | {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1}, |
| 98 | {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, |
| 99 | {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4}, |
| 100 | {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0}, |
| 101 | {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7}, |
| 102 | {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1}, |
| 103 | {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, |
| 104 | {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00}, |
| 105 | // RPR GEC I/O Termination Setting |
| 106 | // PM_Reg 0xF6 = Power-on default setting |
| 107 | // PM_Reg 0xF7 = Power-on default setting |
| 108 | // PM_Reg 0xF8 = 0x6C |
| 109 | // PM_Reg 0xF9 = 0x21 |
| 110 | // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS |
| 111 | {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C}, |
| 112 | {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27}, |
| 113 | {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00}, |
| 114 | {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14}, |
| 115 | {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40}, |
| 116 | |
| 117 | {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR |
| 118 | |
| 119 | {0xFF, 0xFF, 0xFF, 0xFF}, |
| 120 | }; |
| 121 | |
| 122 | /** |
| 123 | * sbPowerOnInit - Config Southbridge during power on stage. |
| 124 | * |
| 125 | * |
| 126 | * |
| 127 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 128 | * |
| 129 | */ |
| 130 | VOID |
| 131 | sbPowerOnInit ( |
| 132 | IN AMDSBCFG* pConfig |
| 133 | ) |
| 134 | { |
| 135 | |
| 136 | UINT8 dbPortStatus; |
| 137 | UINT8 dbSysConfig; |
| 138 | UINT32 abValue; |
| 139 | UINT8 dbValue; |
| 140 | UINT8 dbEfuse; |
| 141 | UINT8 dbCg2WR; |
| 142 | UINT8 dbCg1Pll; |
| 143 | UINT8 cimNbSbGen2; |
| 144 | UINT8 cimSataMode; |
| 145 | UINT8 cimSpiFastReadEnable; |
| 146 | UINT8 cimSpiFastReadSpeed; |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 147 | UINT8 cimSioHwmPortEnable; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 148 | UINT8 SataPortNum; |
| 149 | |
| 150 | cimNbSbGen2 = pConfig->NbSbGen2; |
| 151 | cimSataMode = pConfig->SATAMODE.SataModeReg; |
| 152 | // Adding Fast Read Function support |
Aaron Durbin | d907a34 | 2014-01-30 22:20:01 -0600 | [diff] [blame] | 153 | if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 154 | cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; |
| 155 | } else { |
| 156 | cimSpiFastReadEnable = cimSpiFastReadEnableDefault; |
| 157 | } |
| 158 | cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 159 | cimSioHwmPortEnable = pConfig->SioHwmPortEnable; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 160 | #if SB_CIMx_PARAMETER == 0 |
| 161 | cimNbSbGen2 = cimNbSbGen2Default; |
| 162 | cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); |
| 163 | cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); |
| 164 | cimSpiFastReadEnable = cimSpiFastReadEnableDefault; |
| 165 | cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 166 | cimSioHwmPortEnable = cimSioHwmPortEnableDefault; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 167 | #endif |
| 168 | |
| 169 | // SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct |
| 170 | RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0); |
| 171 | |
| 172 | // Set A-Link bridge access address. This address is set at device 14h, function 0, |
| 173 | // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary. |
| 174 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); |
| 175 | writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction |
| 176 | abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation |
| 177 | abValue = abValue | BIT0; |
| 178 | writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue); |
| 179 | writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. |
| 180 | writeAlink (0x34, readAlink (0x34) | BIT9); |
| 181 | |
| 182 | dbEfuse = FUSE_ID_EFUSE_LOC; |
| 183 | getEfuseStatus (&dbEfuse); |
| 184 | if ( dbEfuse == M1_D1_FUSE_ID ) { |
| 185 | dbEfuse = MINOR_ID_EFUSE_LOC; |
| 186 | getEfuseStatus (&dbEfuse); |
| 187 | if ( dbEfuse == M1_MINOR_ID ) { |
| 188 | // Limit ALink speed to 2.5G if Hudson-M1 |
| 189 | cimNbSbGen2 = 0; |
| 190 | } |
| 191 | } |
| 192 | // Step 1: |
| 193 | // AXINDP_Reg 0xA4[0] = 0x1 |
| 194 | // Step 2: |
| 195 | // AXCFG_Reg 0x88[3:0] = 0x2 |
| 196 | // Step3: |
| 197 | // AXINDP_Reg 0xA4[18] = 0x1 |
| 198 | if ( cimNbSbGen2 == TRUE ) { |
| 199 | rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0); |
| 200 | rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2); |
| 201 | rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18); |
| 202 | } |
| 203 | |
| 204 | // Set Build option into SB |
| 205 | WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 206 | if (cimSioHwmPortEnable) { |
| 207 | // Use Wide IO Port 1 to provide access to the superio HWM registers. |
| 208 | WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); |
| 209 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable |
| 210 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes |
| 211 | } |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 212 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); |
| 213 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); |
| 214 | // Enabled SMBUS0/SMBUS1 (ASF) Base Address |
| 215 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1] |
| 216 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress)); |
| 217 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr)); |
| 218 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr)); |
| 219 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr)); |
| 220 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr)); |
| 221 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr)); |
| 222 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr)); |
| 223 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr)); |
| 224 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8); |
| 225 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase)); |
| 226 | |
| 227 | dbEfuse = SATA_FIS_BASE_EFUSE_LOC; |
| 228 | getEfuseStatus (&dbEfuse); |
| 229 | |
| 230 | programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0])); |
| 231 | |
| 232 | |
| 233 | SataPortNum = 0; |
| 234 | for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) { |
| 235 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum); |
| 236 | SbStall (2); |
| 237 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00); |
| 238 | SbStall (2); |
| 239 | } |
| 240 | |
| 241 | |
| 242 | //The following bits must be set before enabling SPI prefetch. |
| 243 | // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0). |
| 244 | // if Ec is enable |
| 245 | // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed. |
| 246 | // else |
| 247 | // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at |
| 248 | // the speed. |
| 249 | getChipSysMode (&dbSysConfig); |
| 250 | if (pConfig->BuildParameters.SpiSpeed < 0x02) { |
| 251 | pConfig->BuildParameters.SpiSpeed = 0x01; |
| 252 | if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02; |
| 253 | } |
| 254 | |
| 255 | if (pConfig->SbSpiSpeedSupport) { |
| 256 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); |
| 257 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 ); |
| 258 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12)); |
| 259 | } |
| 260 | // SPI Fast Read Function |
| 261 | if ( cimSpiFastReadEnable ) { |
| 262 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18); |
| 263 | } else { |
| 264 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00); |
| 265 | } |
| 266 | |
| 267 | if ( cimSpiFastReadSpeed ) { |
| 268 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); |
| 269 | } |
| 270 | //Program power on pci init table |
| 271 | programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); |
| 272 | |
| 273 | programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); |
| 274 | |
| 275 | dbValue = 0x0A; |
| 276 | WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); |
| 277 | ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); |
| 278 | dbValue &= 0xEF; |
| 279 | WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); |
| 280 | |
| 281 | // Change the CG PLL multiplier to x1.1 |
| 282 | if ( pConfig->UsbRxMode !=0 ) { |
| 283 | dbCg2WR = 0x00; |
| 284 | dbCg1Pll = 0x3A; |
| 285 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR); |
| 286 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); |
| 287 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll); |
| 288 | dbCg2WR &= BIT4; |
| 289 | if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 )) |
| 290 | { |
| 291 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10); |
| 292 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); |
| 293 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage); |
| 294 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10); |
| 295 | dbValue = 0x06; |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 296 | WriteIO (0xCF9, AccWidthUint8, &dbValue); |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 297 | } else { |
| 298 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0); |
| 303 | |
| 304 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD ); |
| 305 | |
| 306 | if (dbEfuse & BIT0) { |
| 307 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); |
| 308 | } |
| 309 | |
| 310 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus); |
| 311 | if ( ((dbPortStatus & 0xF0) == 0x10) ) { |
| 312 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5); |
| 313 | } |
| 314 | |
| 315 | if ( pConfig->BuildParameters.LegacyFree ) { |
| 316 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); |
| 317 | } else { |
| 318 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); |
| 319 | } |
| 320 | |
| 321 | dbValue = 0x09; |
| 322 | WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); |
| 323 | ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 324 | if ( !pConfig->BuildParameters.EcKbd ) { |
| 325 | // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input |
| 326 | dbValue = dbValue & 0xF9; |
| 327 | } |
| 328 | if ( pConfig->BuildParameters.LegacyFree ) { |
| 329 | // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. |
| 330 | dbValue = dbValue & 0x9F; |
| 331 | } |
| 332 | // Enabled IRQ input |
| 333 | dbValue = dbValue | BIT4; |
| 334 | WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 335 | |
| 336 | #ifndef NO_EC_SUPPORT |
| 337 | getChipSysMode (&dbPortStatus); |
| 338 | if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) { |
| 339 | // EC is disabled by jumper setting or board config |
| 340 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); |
| 341 | } else { |
| 342 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08); |
| 343 | ecPowerOnInit ( pConfig); |
| 344 | } |
| 345 | #endif |
| 346 | |
| 347 | ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue); |
| 348 | if (dbValue & ChipSysIntClkGen) { |
| 349 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue); |
| 350 | if (dbValue & BIT2) { |
| 351 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); |
| 352 | } else { |
| 353 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40); |
| 354 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); |
| 355 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00); |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | // Restore GPP clock to on as it may be off during last POST when some device was disabled; |
| 360 | // the device can't be detected if enabled again as the values retain on S5 and warm reset. |
| 361 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF); |
| 362 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF); |
| 363 | |
| 364 | // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation |
| 365 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 366 | } |