Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /** |
| 2 | * @file |
| 3 | * |
| 4 | * Southbridge IO access common routine |
| 5 | * |
| 6 | * |
| 7 | * |
| 8 | * @xrefitem bom "File Content Label" "Release Content" |
| 9 | * @e project: CIMx-SB |
| 10 | * @e sub-project: |
| 11 | * @e \$Revision:$ @e \$Date:$ |
| 12 | * |
| 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 19 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 29 | * from this software without specific prior written permission. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 30 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 41 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #include "SBPLATFORM.h" |
| 47 | #include "cbtypes.h" |
| 48 | |
| 49 | /** |
| 50 | * Read Southbridge Revision ID cie Base |
| 51 | * |
| 52 | * |
| 53 | * @retval 0xXXXXXXXX Revision ID |
| 54 | * |
| 55 | */ |
| 56 | UINT8 |
| 57 | getRevisionID ( |
| 58 | OUT VOID |
| 59 | ) |
| 60 | { |
| 61 | UINT8 dbVar0; |
| 62 | ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0); |
| 63 | return dbVar0; |
| 64 | } |
| 65 | |
| 66 | /*----------------------------------------------------------------------------------------*/ |
| 67 | /** |
| 68 | * programPciByteTable - Program PCI register by table (8 bits data) |
| 69 | * |
| 70 | * |
| 71 | * |
| 72 | * @param[in] pPciByteTable - Table data pointer |
| 73 | * @param[in] dwTableSize - Table length |
| 74 | * |
| 75 | */ |
| 76 | VOID |
| 77 | programPciByteTable ( |
| 78 | IN REG8MASK* pPciByteTable, |
| 79 | IN UINT16 dwTableSize |
| 80 | ) |
| 81 | { |
| 82 | UINT8 i; |
| 83 | UINT8 dbBusNo; |
| 84 | UINT8 dbDevFnNo; |
| 85 | UINT32 ddBDFR; |
| 86 | |
| 87 | dbBusNo = pPciByteTable->bRegIndex; |
| 88 | dbDevFnNo = pPciByteTable->bANDMask; |
| 89 | pPciByteTable++; |
| 90 | |
| 91 | for ( i = 1; i < dwTableSize; i++ ) { |
| 92 | if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) { |
| 93 | pPciByteTable++; |
| 94 | dbBusNo = pPciByteTable->bRegIndex; |
| 95 | dbDevFnNo = pPciByteTable->bANDMask; |
| 96 | pPciByteTable++; |
| 97 | i++; |
| 98 | } else { |
| 99 | ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; |
| 100 | RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); |
| 101 | pPciByteTable++; |
| 102 | } |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | /*----------------------------------------------------------------------------------------*/ |
| 107 | /** |
| 108 | * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) |
| 109 | * |
| 110 | * |
| 111 | * |
| 112 | * @param[in] pAcpiTbl - Table data pointer |
| 113 | * |
| 114 | */ |
| 115 | VOID |
| 116 | programSbAcpiMmioTbl ( |
| 117 | IN AcpiRegWrite *pAcpiTbl |
| 118 | ) |
| 119 | { |
| 120 | UINT8 i; |
| 121 | UINT32 ddtempVar; |
| 122 | if (pAcpiTbl != NULL) { |
| 123 | for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) { |
| 124 | ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; |
| 125 | RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask); |
| 126 | pAcpiTbl++; |
| 127 | } |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | /** |
| 132 | * getChipSysMode - Get Chip status |
| 133 | * |
| 134 | * |
| 135 | * @param[in] Value - Return Chip strap status |
| 136 | * StrapStatus [15.0] - SB800 chip Strap Status |
| 137 | * @li <b>0001</b> - Not USED FWH |
| 138 | * @li <b>0002</b> - Not USED LPC ROM |
| 139 | * @li <b>0004</b> - EC enabled |
| 140 | * @li <b>0008</b> - Reserved |
| 141 | * @li <b>0010</b> - Internal Clock mode |
| 142 | * |
| 143 | */ |
| 144 | VOID |
| 145 | getChipSysMode ( |
| 146 | IN VOID* Value |
| 147 | ) |
| 148 | { |
| 149 | ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value); |
| 150 | } |
| 151 | |
| 152 | /*----------------------------------------------------------------------------------------*/ |
| 153 | /** |
| 154 | * Read Southbridge CIMx configuration structure pointer |
| 155 | * |
| 156 | * |
| 157 | * |
| 158 | * @retval 0xXXXXXXXX CIMx configuration structure pointer. |
| 159 | * |
| 160 | */ |
| 161 | AMDSBCFG* |
| 162 | getConfigPointer ( |
| 163 | OUT VOID |
| 164 | ) |
| 165 | { |
| 166 | UINT8 dbReg; |
| 167 | UINT8 dbValue; |
| 168 | UINT8 i; |
| 169 | UINT32 ddValue; |
| 170 | ddValue = 0; |
| 171 | dbReg = SB_ECMOS_REG08; |
| 172 | |
| 173 | for ( i = 0; i <= 3; i++ ) { |
| 174 | WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); |
| 175 | ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue); |
| 176 | ddValue |= (dbValue << (i * 8)); |
| 177 | dbReg++; |
| 178 | } |
| 179 | return ( (AMDSBCFG*) (UINTN)ddValue); |
| 180 | } |
| 181 | |
| 182 | /** |
| 183 | * getEfuseStatue - Get Efuse status |
| 184 | * |
| 185 | * |
| 186 | * @param[in] Value - Return Chip strap status |
| 187 | * |
| 188 | */ |
| 189 | VOID |
| 190 | getEfuseStatus ( |
| 191 | IN VOID* Value |
| 192 | ) |
| 193 | { |
| 194 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5); |
| 195 | WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value); |
| 196 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value); |
| 197 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0); |
| 198 | } |