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review.coreboot.org / coreboot / 4e9bb3308e811000eb089be6b03658e4cb9a4717 / . / src / vendorcode / amd / agesa / f15tn / Config / OptionFchInstall.h
blob: 5ea5fd15950b9247b1b8c05f7d64ebf097249d0c [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of family 15h support
6 *
7 * This file generates the defaults tables for family 15h processors.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Core
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 */
14/*********************************************************************************
15;
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]16 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]40;*********************************************************************************/
41
42#ifndef _OPTION_FCH_INSTALL_H_
43#define _OPTION_FCH_INSTALL_H_
44
Alexandru Gagniuc986349d2014-03-29 16:52:46 -0500[diff] [blame]45#include <Proc/Common/AmdFch.h>
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]46
47#ifndef FCH_SUPPORT
48 #define FCH_SUPPORT FALSE
49#endif
50
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame]51/* Define the default values for the FCH configuration settings */
52#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
53#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
54/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
55#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
56#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
57#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
58#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
59#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
60#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
61#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
62#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
63#define DFLT_HPET_BASE_ADDRESS 0xFED00000
64#define DFLT_SMI_CMD_PORT 0xB0
65#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
66#define DFLT_GEC_BASE_ADDRESS 0xFED61000
67#define DFLT_AZALIA_SSID 0x780D1022
68#define DFLT_SMBUS_SSID 0x780B1022
69#define DFLT_IDE_SSID 0x780C1022
70#define DFLT_SATA_AHCI_SSID 0x78011022
71#define DFLT_SATA_IDE_SSID 0x78001022
72#define DFLT_SATA_RAID5_SSID 0x78031022
73#define DFLT_SATA_RAID_SSID 0x78021022
74#define DFLT_EHCI_SSID 0x78081022
75#define DFLT_OHCI_SSID 0x78071022
76#define DFLT_LPC_SSID 0x780E1022
77#define DFLT_SD_SSID 0x78061022
78#define DFLT_XHCI_SSID 0x78121022
79#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
80#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
81
82#define DFLT_FCH_GPP_LINK_CONFIG PortA4
83#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
84#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
85#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
86#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
87
88#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
89#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
90#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
91#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]92
93/* ACPI block register offset definitions */
94#define PM1_STATUS_OFFSET 0x00
95#define PM1_ENABLE_OFFSET 0x02
96#define PM_CONTROL_OFFSET 0x04
97#define PM_TIMER_OFFSET 0x08
98#define CPU_CONTROL_OFFSET 0x10
99#define EVENT_STATUS_OFFSET 0x20
100#define EVENT_ENABLE_OFFSET 0x24
101
102
103#if FCH_SUPPORT == TRUE
104 /*
105 * FCH subfunctions
106 */
107 #ifdef AGESA_ENTRY_INIT_RESET
108 #if AGESA_ENTRY_INIT_RESET == TRUE
109 extern FCH_TASK_ENTRY FchInitResetHwAcpiP;
110 extern FCH_TASK_ENTRY FchInitResetHwAcpi;
111 extern FCH_TASK_ENTRY FchInitResetAb;
112 extern FCH_TASK_ENTRY FchInitResetSpi;
113 extern FCH_TASK_ENTRY FchInitResetGec;
114 extern FCH_TASK_ENTRY FchInitResetSata;
115 extern FCH_TASK_ENTRY FchInitResetLpc;
116 extern FCH_TASK_ENTRY FchInitResetPcib;
117 extern FCH_TASK_ENTRY FchInitResetPcie;
118 extern FCH_TASK_ENTRY FchInitResetGpp;
119 extern FCH_TASK_ENTRY FchInitResetUsb;
120 extern FCH_TASK_ENTRY FchInitResetEhci;
121 extern FCH_TASK_ENTRY FchInitResetOhci;
122 extern FCH_TASK_ENTRY FchInitResetXhci;
123 extern FCH_TASK_ENTRY FchInitResetImc;
124 #endif
125 #endif
126
127 #ifdef AGESA_ENTRY_INIT_ENV
128 #if AGESA_ENTRY_INIT_ENV == TRUE
129 extern FCH_TASK_ENTRY FchInitEnvUsbXhci;
130 extern FCH_TASK_ENTRY FchInitEnvUsbOhci;
131 extern FCH_TASK_ENTRY FchInitEnvUsbEhci;
132 extern FCH_TASK_ENTRY FchInitEnvUsb;
133 extern FCH_TASK_ENTRY FchInitEnvAb;
134 extern FCH_TASK_ENTRY FchInitEnvGpp;
135 extern FCH_TASK_ENTRY FchInitEnvGppPhaseII;
136 extern FCH_TASK_ENTRY FchInitEnvPcie;
137 extern FCH_TASK_ENTRY FchInitEnvPcib;
138 extern FCH_TASK_ENTRY FchInitEnvHwAcpiP;
139 extern FCH_TASK_ENTRY FchInitEnvHwAcpi;
140 extern FCH_TASK_ENTRY FchInitEnvAbSpecial;
141 extern FCH_TASK_ENTRY FchInitEnvSpi;
142 extern FCH_TASK_ENTRY FchInitEnvGec;
143 extern FCH_TASK_ENTRY FchInitEnvSata;
144 extern FCH_TASK_ENTRY FchInitEnvIde;
145 extern FCH_TASK_ENTRY FchInitEnvSd;
146 extern FCH_TASK_ENTRY FchInitEnvIr;
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]147 extern FCH_TASK_ENTRY FchInitEnvAzalia;
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]148 extern FCH_TASK_ENTRY FchInitEnvHwm;
149 extern FCH_TASK_ENTRY FchInitEnvImc;
150 #endif
151 #endif
152
153 #ifdef AGESA_ENTRY_INIT_MID
154 #if AGESA_ENTRY_INIT_MID == TRUE
155 extern FCH_TASK_ENTRY FchInitMidHwm;
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]156 extern FCH_TASK_ENTRY FchInitMidAzalia;
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]157 extern FCH_TASK_ENTRY FchInitMidGec;
158 extern FCH_TASK_ENTRY FchInitMidSata;
159 extern FCH_TASK_ENTRY FchInitMidIde;
160 extern FCH_TASK_ENTRY FchInitMidAb;
161 extern FCH_TASK_ENTRY FchInitMidUsb;
162 extern FCH_TASK_ENTRY FchInitMidUsbEhci;
163 extern FCH_TASK_ENTRY FchInitMidUsbOhci;
164 extern FCH_TASK_ENTRY FchInitMidUsbXhci;
165 extern FCH_TASK_ENTRY FchInitMidImc;
166 #endif
167 #endif
168
169 #ifdef AGESA_ENTRY_INIT_LATE
170 #if AGESA_ENTRY_INIT_LATE == TRUE
171 extern FCH_TASK_ENTRY FchInitLateHwAcpi;
172 extern FCH_TASK_ENTRY FchInitLateSpi;
173 extern FCH_TASK_ENTRY FchInitLateGec;
174 extern FCH_TASK_ENTRY FchInitLateSata;
175 extern FCH_TASK_ENTRY FchInitLateIde;
176 extern FCH_TASK_ENTRY FchInitLatePcib;
177 extern FCH_TASK_ENTRY FchInitLateAb;
178 extern FCH_TASK_ENTRY FchInitLatePcie;
179 extern FCH_TASK_ENTRY FchInitLateGpp;
180 extern FCH_TASK_ENTRY FchInitLateUsb;
181 extern FCH_TASK_ENTRY FchInitLateUsbEhci;
182 extern FCH_TASK_ENTRY FchInitLateUsbOhci;
183 extern FCH_TASK_ENTRY FchInitLateUsbXhci;
184 extern FCH_TASK_ENTRY FchInitLateImc;
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]185 extern FCH_TASK_ENTRY FchInitLateAzalia;
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]186 extern FCH_TASK_ENTRY FchInitLateHwm;
187 #endif
188 #endif
189
190 extern FCH_TASK_ENTRY FchTaskDummy;
191 extern FCH_TASK_ENTRY FchGppHotplugSmiCallback;
192 /* FCH Interface entries */
193 extern FCH_INIT CommonFchInitStub;
194
195 /* FCH Interface entries */
196 #ifdef AGESA_ENTRY_INIT_RESET
197 #if AGESA_ENTRY_INIT_RESET == TRUE
198 extern FCH_INIT FchInitReset;
199 extern FCH_INIT FchResetConstructor;
200
201 #define FP_FCH_INIT_RESET &FchInitReset
202 #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor
203 #else
204 #define FP_FCH_INIT_RESET &CommonFchInitStub
205 #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
206 #endif
207 #endif
208
209 #ifdef AGESA_ENTRY_INIT_ENV
210 #if AGESA_ENTRY_INIT_ENV == TRUE
211 extern FCH_INIT FchInitEnv;
212 extern FCH_INIT FchEnvConstructor;
213
214 #define FP_FCH_INIT_ENV &FchInitEnv
215 #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor
216 #else
217 #define FP_FCH_INIT_ENV &CommonFchInitStub
218 #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
219 #endif
220 #endif
221
222 #ifdef AGESA_ENTRY_INIT_MID
223 #if AGESA_ENTRY_INIT_MID == TRUE
224 extern FCH_INIT FchInitMid;
225 extern FCH_INIT FchMidConstructor;
226
227 #define FP_FCH_INIT_MID &FchInitMid
228 #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor
229 #else
230 #define FP_FCH_INIT_MID &CommonFchInitStub
231 #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
232 #endif
233 #endif
234
235 #ifdef AGESA_ENTRY_INIT_LATE
236 #if AGESA_ENTRY_INIT_LATE == TRUE
237 extern FCH_INIT FchInitLate;
238 extern FCH_INIT FchLateConstructor;
239
240 #define FP_FCH_INIT_LATE &FchInitLate
241 #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor
242 #else
243 #define FP_FCH_INIT_LATE &CommonFchInitStub
244 #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
245 #endif
246 #endif
247
248 /* FCH subcomponent build options */
249 #undef FCH_NO_HWACPI_SUPPORT
250 #undef FCH_NO_AB_SUPPORT
251 #undef FCH_NO_SPI_SUPPORT
252 #undef FCH_NO_GEC_SUPPORT
253 #undef FCH_NO_SATA_SUPPORT
254 #undef FCH_NO_IDE_SUPPORT
255 #undef FCH_NO_LPC_SUPPORT
256 #undef FCH_NO_PCIB_SUPPORT
257 #undef FCH_NO_PCIE_SUPPORT
258 #undef FCH_NO_GPP_SUPPORT
259 #undef FCH_NO_USB_SUPPORT
260 #undef FCH_NO_EHCI_SUPPORT
261 #undef FCH_NO_OHCI_SUPPORT
262 #undef FCH_NO_XHCI_SUPPORT
263 #undef FCH_NO_IMC_SUPPORT
264 #undef FCH_NO_SD_SUPPORT
265 #undef FCH_NO_IR_SUPPORT
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]266 #undef FCH_NO_AZALIA_SUPPORT
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]267 #undef FCH_NO_HWM_SUPPORT
268
269 #define FCH_NO_GEC_SUPPORT TRUE
270
271 // Following are determined by silicon characteristics
272 #if (OPTION_FAMILY15H_TN == TRUE)
273 //#define FCH_NO_GEC_SUPPORT TRUE
274 #else
275 #if (OPTION_FAMILY14H_ON == TRUE)
276 #define FCH_NO_XHCI_SUPPORT TRUE
277 #else
278 #error FCH_SUPPORT: No chip type selected.
279 #endif
280 #endif
281 //
282 // Installable blocks depending on build switches
283 //
284 #ifndef FCH_NO_HWACPI_SUPPORT
285 #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI)
286 #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP
287 #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi
288 #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP
289 #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi
290 #define InstallFchInitMidHwAcpi &FchTaskDummy
291 #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi
292 #else
293 #define BLOCK_HWACPI_SIZE 0
294 #define InstallFchInitResetHwAcpiP &FchTaskDummy
295 #define InstallFchInitResetHwAcpi &FchTaskDummy
296 #define InstallFchInitEnvHwAcpi &FchTaskDummy
297 #define InstallFchInitMidHwAcpi &FchTaskDummy
298 #define InstallFchInitLateHwAcpi &FchTaskDummy
299 #endif
300
301 #ifndef FCH_NO_AB_SUPPORT
302 #define BLOCK_AB_SIZE sizeof (FCH_AB)
303 #define InstallFchInitResetAb &FchInitResetAb
304 #define InstallFchInitEnvAb &FchInitEnvAb
305 #define InstallFchInitEnvAbS &FchInitEnvAbSpecial
306 #define InstallFchInitMidAb &FchInitMidAb
307 #define InstallFchInitLateAb &FchInitLateAb
308 #else
309 #define BLOCK_AB_SIZE 0
310 #define InstallFchInitResetAb &FchTaskDummy
311 #define InstallFchInitEnvAb &FchTaskDummy
312 #define InstallFchInitEnvAbS &FchTaskDummy
313 #define InstallFchInitMidAb &FchTaskDummy
314 #define InstallFchInitLateAb &FchTaskDummy
315 #endif
316
317 #ifndef FCH_NO_SPI_SUPPORT
318 #define BLOCK_SPI_SIZE sizeof (FCH_SPI)
319 #define InstallFchInitResetSpi &FchInitResetSpi
320 #define InstallFchInitEnvSpi &FchInitEnvSpi
321 #define InstallFchInitMidSpi &FchTaskDummy
322 #define InstallFchInitLateSpi &FchInitLateSpi
323 #else
324 #define BLOCK_SPI_SIZE 0
325 #define InstallFchInitResetSpi &FchTaskDummy
326 #define InstallFchInitEnvSpi &FchTaskDummy
327 #define InstallFchInitMidSpi &FchTaskDummy
328 #define InstallFchInitLateSpi &FchTaskDummy
329 #endif
330
331 #ifndef FCH_NO_GEC_SUPPORT
332 #define BLOCK_GEC_SIZE sizeof (FCH_GEC)
333 #define InstallFchInitResetGec &FchInitResetGec
334 #define InstallFchInitEnvGec &FchInitEnvGec
335 #define InstallFchInitMidGec &FchInitMidGec
336 #define InstallFchInitLateGec &FchInitLateGec
337 #else
338 #define BLOCK_GEC_SIZE 0
339 #define InstallFchInitResetGec &FchTaskDummy
340 #define InstallFchInitEnvGec &FchTaskDummy
341 #define InstallFchInitMidGec &FchTaskDummy
342 #define InstallFchInitLateGec &FchTaskDummy
343 #endif
344
345 #ifndef FCH_NO_SATA_SUPPORT
346 #define BLOCK_SATA_SIZE sizeof (FCH_SATA)
347 #define InstallFchInitResetSata &FchInitResetSata
348 #define InstallFchInitEnvSata &FchInitEnvSata
349 #define InstallFchInitMidSata &FchInitMidSata
350 #define InstallFchInitLateSata &FchInitLateSata
351 #else
352 #define BLOCK_SATA_SIZE 0
353 #define InstallFchInitResetSata &FchTaskDummy
354 #define InstallFchInitEnvSata &FchTaskDummy
355 #define InstallFchInitMidSata &FchTaskDummy
356 #define InstallFchInitLateSata &FchTaskDummy
357 #endif
358
359 #ifndef FCH_NO_IDE_SUPPORT
360 #define BLOCK_IDE_SIZE sizeof (FCH_IDE)
361 #define InstallFchInitResetIde &FchTaskDummy
362 #define InstallFchInitEnvIde &FchInitEnvIde
363 #define InstallFchInitMidIde &FchInitMidIde
364 #define InstallFchInitLateIde &FchInitLateIde
365 #else
366 #define BLOCK_IDE_SIZE 0
367 #define InstallFchInitResetIde &FchTaskDummy
368 #define InstallFchInitEnvIde &FchTaskDummy
369 #define InstallFchInitMidIde &FchTaskDummy
370 #define InstallFchInitLateIde &FchTaskDummy
371 #endif
372
373 #ifndef FCH_NO_LPC_SUPPORT
374 #define BLOCK_LPC_SIZE sizeof (FCH_LPC)
375 #define InstallFchInitResetLpc &FchInitResetLpc
376 #define InstallFchInitEnvLpc &FchTaskDummy
377 #define InstallFchInitMidLpc &FchTaskDummy
378 #define InstallFchInitLateLpc &FchTaskDummy
379 #else
380 #define BLOCK_LPC_SIZE 0
381 #define InstallFchInitResetLpc &FchTaskDummy
382 #define InstallFchInitEnvLpc &FchTaskDummy
383 #define InstallFchInitMidLpc &FchTaskDummy
384 #define InstallFchInitLateLpc &FchTaskDummy
385 #endif
386
387 #ifndef FCH_NO_PCIB_SUPPORT
388 #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB)
389 #define InstallFchInitResetPcib &FchInitResetPcib
390 #define InstallFchInitEnvPcib &FchInitEnvPcib
391 #define InstallFchInitMidPcib &FchTaskDummy
392 #define InstallFchInitLatePcib &FchInitLatePcib
393 #else
394 #define BLOCK_PCIB_SIZE 0
395 #define InstallFchInitResetPcib &FchTaskDummy
396 #define InstallFchInitEnvPcib &FchTaskDummy
397 #define InstallFchInitMidPcib &FchTaskDummy
398 #define InstallFchInitLatePcib &FchTaskDummy
399 #endif
400
401 #ifndef FCH_NO_PCIE_SUPPORT
402 #define InstallFchInitResetPcie &FchInitResetPcie
403 #define InstallFchInitEnvPcie &FchInitEnvPcie
404 #define InstallFchInitMidPcie &FchTaskDummy
405 #define InstallFchInitLatePcie &FchInitLatePcie
406 #else
407 #define InstallFchInitResetPcie &FchTaskDummy
408 #define InstallFchInitEnvPcie &FchTaskDummy
409 #define InstallFchInitMidPcie &FchTaskDummy
410 #define InstallFchInitLatePcie &FchTaskDummy
411 #endif
412
413 #ifndef FCH_NO_GPP_SUPPORT
414 #define BLOCK_GPP_SIZE sizeof (FCH_GPP)
415 #define InstallFchInitResetGpp &FchInitResetGpp
416 #define InstallFchInitEnvGpp &FchInitEnvGpp
417 #define InstallFchInitEnvGppPhaseII &FchInitEnvGppPhaseII
418 #define InstallFchInitMidGpp &FchTaskDummy
419 #define InstallFchInitLateGpp &FchInitLateGpp
420 #define InstallHpSmiCallback &FchGppHotplugSmiCallback
421 #else
422 #define BLOCK_GPP_SIZE 0
423 #define InstallFchInitResetGpp &FchTaskDummy
424 #define InstallFchInitEnvGpp &FchTaskDummy
425 #define InstallFchInitEnvGppPhaseII &FchTaskDummy
426 #define InstallFchInitMidGpp &FchTaskDummy
427 #define InstallFchInitLateGpp &FchTaskDummy
428 #define InstallHpSmiCallback &FchTaskDummy
429 #endif
430
431 #ifndef FCH_NO_USB_SUPPORT
432 #define BLOCK_USB_SIZE sizeof (FCH_USB)
433 #define InstallFchInitResetUsb &FchInitResetUsb
434 #define InstallFchInitEnvUsb &FchInitEnvUsb
435 #define InstallFchInitMidUsb &FchInitMidUsb
436 #define InstallFchInitLateUsb &FchInitLateUsb
437 #else
438 #define BLOCK_USB_SIZE 0
439 #define InstallFchInitResetUsb &FchTaskDummy
440 #define InstallFchInitEnvUsb &FchTaskDummy
441 #define InstallFchInitMidUsb &FchTaskDummy
442 #define InstallFchInitLateUsb &FchTaskDummy
443 #endif
444
445 #ifndef FCH_NO_EHCI_SUPPORT
446 #define InstallFchInitResetUsbEhci &FchInitResetEhci
447 #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci
448 #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci
449 #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci
450 #else
451 #define InstallFchInitResetUsbEhci &FchTaskDummy
452 #define InstallFchInitEnvUsbEhci &FchTaskDummy
453 #define InstallFchInitMidUsbEhci &FchTaskDummy
454 #define InstallFchInitLateUsbEhci &FchTaskDummy
455 #endif
456
457 #ifndef FCH_NO_OHCI_SUPPORT
458 #define InstallFchInitResetUsbOhci &FchInitResetOhci
459 #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci
460 #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci
461 #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci
462 #else
463 #define InstallFchInitResetUsbOhci &FchTaskDummy
464 #define InstallFchInitEnvUsbOhci &FchTaskDummy
465 #define InstallFchInitMidUsbOhci &FchTaskDummy
466 #define InstallFchInitLateUsbOhci &FchTaskDummy
467 #endif
468
469 #ifndef FCH_NO_XHCI_SUPPORT
470 #define InstallFchInitResetUsbXhci &FchInitResetXhci
471 #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci
472 #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci
473 #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci
474 #else
475 #define InstallFchInitResetUsbXhci &FchTaskDummy
476 #define InstallFchInitEnvUsbXhci &FchTaskDummy
477 #define InstallFchInitMidUsbXhci &FchTaskDummy
478 #define InstallFchInitLateUsbXhci &FchTaskDummy
479 #endif
480
481 #ifndef FCH_NO_IMC_SUPPORT
482 #define BLOCK_IMC_SIZE sizeof (FCH_IMC)
483 #define InstallFchInitResetImc &FchInitResetImc
484 #define InstallFchInitEnvImc &FchInitEnvImc
485 #define InstallFchInitMidImc &FchInitMidImc
486 #define InstallFchInitLateImc &FchInitLateImc
487 #else
488 #define BLOCK_IMC_SIZE 0
489 #define InstallFchInitResetImc &FchTaskDummy
490 #define InstallFchInitEnvImc &FchTaskDummy
491 #define InstallFchInitMidImc &FchTaskDummy
492 #define InstallFchInitLateImc &FchTaskDummy
493 #endif
494
495
496 #ifndef FCH_NO_SD_SUPPORT
497 #define BLOCK_SD_SIZE sizeof (FCH_SD)
498 #define InstallFchInitResetSd &FchTaskDummy
499 #define InstallFchInitEnvSd &FchInitEnvSd
500 #define InstallFchInitMidSd &FchTaskDummy
501 #define InstallFchInitLateSd &FchTaskDummy
502 #else
503 #define BLOCK_SD_SIZE 0
504 #define InstallFchInitResetSd &FchTaskDummy
505 #define InstallFchInitEnvSd &FchTaskDummy
506 #define InstallFchInitMidSd &FchTaskDummy
507 #define InstallFchInitLateSd &FchTaskDummy
508 #endif
509
510 #ifndef FCH_NO_IR_SUPPORT
511 #define BLOCK_IR_SIZE sizeof (FCH_IR)
512 #define InstallFchInitResetIr &FchTaskDummy
513 #define InstallFchInitEnvIr &FchInitEnvIr
514 #define InstallFchInitMidIr &FchTaskDummy
515 #define InstallFchInitLateIr &FchTaskDummy
516 #else
517 #define BLOCK_IR_SIZE 0
518 #define InstallFchInitResetIr &FchTaskDummy
519 #define InstallFchInitEnvIr &FchTaskDummy
520 #define InstallFchInitMidIr &FchTaskDummy
521 #define InstallFchInitLateIr &FchTaskDummy
522 #endif
523
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]524 #ifndef FCH_NO_AZALIA_SUPPORT
525 #define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA)
526 #define InstallFchInitResetAzalia &FchInitResetAzalia
527 #define InstallFchInitEnvAzalia &FchInitEnvAzalia
528 #define InstallFchInitMidAzalia &FchInitMidAzalia
529 #define InstallFchInitLateAzalia &FchInitLateAzalia
530 #else
531 #define BLOCK_AZALIA_SIZE 0
532 #define InstallFchInitResetAzalia &FchTaskDummy
533 #define InstallFchInitEnvAzalia &FchTaskDummy
534 #define InstallFchInitMidAzalia &FchTaskDummy
535 #define InstallFchInitLateAzalia &FchTaskDummy
536 #endif
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]537
538 #ifndef FCH_NO_HWM_SUPPORT
539 #define BLOCK_HWM_SIZE sizeof (FCH_HWM)
540 #define InstallFchInitResetHwm &FchTaskDummy
541 #define InstallFchInitEnvHwm &FchTaskDummy
542 #define InstallFchInitMidHwm &FchTaskDummy
543 #define InstallFchInitLateHwm &FchInitLateHwm
544 #else
545 #define InstallFchInitResetHwm &FchTaskDummy
546 #define InstallFchInitEnvHwm &FchTaskDummy
547 #define InstallFchInitMidHwm &FchTaskDummy
548 #define InstallFchInitLateHwm &FchTaskDummy
549 #endif
550
551
552 #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS)
553 #define BLOCK_HPET_SIZE sizeof (FCH_HPET)
554 #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU)
555 #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB)
556 #define BLOCK_MISC_SIZE sizeof (FCH_MISC)
557
558
559 // Optionally declare OEM hooks after each phase
560 #ifndef FCH_INIT_RESET_HOOK
561 #define InstallFchInitResetHook FchTaskDummy
562 #else
563 #define InstallFchInitResetHook OemFchInitResetHook
564 #endif
565
566
567 //
568 // Define FCH build time options and configurations
569 //
570 #ifdef BLDCFG_SMBUS0_BASE_ADDRESS
571 #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS
572 #else
573 #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS
574 #endif
575
576 #ifdef BLDCFG_SMBUS1_BASE_ADDRESS
577 #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS
578 #else
579 #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS
580 #endif
581
582 #ifdef BLDCFG_SIO_PME_BASE_ADDRESS
583 #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS
584 #else
585 #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS
586 #endif
587
588 #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
589 #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
590 #else
591 #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
592 #endif
593 #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
594 #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
595 #else
596 #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
597 #endif
598 #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
599 #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
600 #else
601 #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
602 #endif
603 #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
604 #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
605 #else
606 #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
607 #endif
608 #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
609 #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
610 #else
611 #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS
612 #endif
613
614
615 #ifdef BLDCFG_WATCHDOG_TIMER_BASE
616 #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE
617 #else
618 #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS
619 #endif
620
621 #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
622 #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS
623 #else
624 #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS
625 #endif
626
627 #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
628 #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS
629 #else
630 #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT
631 #endif
632
633 #ifdef BLDCFG_ROM_BASE_ADDRESS
634 #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS
635 #else
636 #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS
637 #endif
638
639 #ifdef BLDCFG_GEC_SHADOW_ROM_BASE
640 #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE
641 #else
642 #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS
643 #endif
644
645 #ifdef BLDCFG_HPET_BASE_ADDRESS
646 #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS
647 #else
648 #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS
649 #endif
650
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]651 #ifdef BLDCFG_AZALIA_SSID
652 #define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID
653 #else
654 #define CFG_AZALIA_SSID DFLT_AZALIA_SSID
655 #endif
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]656
657 #ifdef BLDCFG_SMBUS_SSID
658 #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID
659 #else
660 #define CFG_SMBUS_SSID DFLT_SMBUS_SSID
661 #endif
662
663 #ifdef BLDCFG_IDE_SSID
664 #define CFG_IDE_SSID BLDCFG_IDE_SSID
665 #else
666 #define CFG_IDE_SSID DFLT_IDE_SSID
667 #endif
668
669 #ifdef BLDCFG_SATA_AHCI_SSID
670 #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID
671 #else
672 #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID
673 #endif
674
675 #ifdef BLDCFG_SATA_IDE_SSID
676 #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID
677 #else
678 #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID
679 #endif
680
681 #ifdef BLDCFG_SATA_RAID5_SSID
682 #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID
683 #else
684 #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID
685 #endif
686
687 #ifdef BLDCFG_SATA_RAID_SSID
688 #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID
689 #else
690 #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID
691 #endif
692
693 #ifdef BLDCFG_EHCI_SSID
694 #define CFG_EHCI_SSID BLDCFG_EHCI_SSID
695 #else
696 #define CFG_EHCI_SSID DFLT_EHCI_SSID
697 #endif
698
699 #ifdef BLDCFG_OHCI_SSID
700 #define CFG_OHCI_SSID BLDCFG_OHCI_SSID
701 #else
702 #define CFG_OHCI_SSID DFLT_OHCI_SSID
703 #endif
704
705 #ifdef BLDCFG_LPC_SSID
706 #define CFG_LPC_SSID BLDCFG_LPC_SSID
707 #else
708 #define CFG_LPC_SSID DFLT_LPC_SSID
709 #endif
710
711 #ifdef BLDCFG_SD_SSID
712 #define CFG_SD_SSID BLDCFG_SD_SSID
713 #else
714 #define CFG_SD_SSID DFLT_SD_SSID
715 #endif
716
717 #ifdef BLDCFG_XHCI_SSID
718 #define CFG_XHCI_SSID BLDCFG_XHCI_SSID
719 #else
720 #define CFG_XHCI_SSID DFLT_XHCI_SSID
721 #endif
722
723 #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
724 #define CFG_FCH_PORT80_BEHIND_PCIB BLDCFG_FCH_PORT80_BEHIND_PCIB
725 #else
726 #define CFG_FCH_PORT80_BEHIND_PCIB DFLT_FCH_PORT80_BEHIND_PCIB
727 #endif
728
729 #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
730 #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
731 #else
732 #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
733 #endif
734
735 #ifdef BLDCFG_FCH_GPP_LINK_CONFIG
736 #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG
737 #else
738 #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG
739 #endif
740
741 #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
742 #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT
743 #else
744 #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT
745 #endif
746
747 #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
748 #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT
749 #else
750 #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT
751 #endif
752
753 #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
754 #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT
755 #else
756 #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT
757 #endif
758
759 #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
760 #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT
761 #else
762 #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT
763 #endif
764
765 #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
766 #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG
767 #else
768 #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG
769 #endif
770
771 #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
772 #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG
773 #else
774 #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG
775 #endif
776
777 #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
778 #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG
779 #else
780 #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG
781 #endif
782
783 #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
784 #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG
785 #else
786 #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG
787 #endif
788
789 #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
790 #define CFG_FCH_ESATA_PORT_BITMAP BLDCFG_FCH_ESATA_PORT_BITMAP
791 #else
792 #define CFG_FCH_ESATA_PORT_BITMAP 0
793 #endif
794
795 #ifdef BLDCFG_FCH_IR_PIN_CONTROL
796 #define CFG_FCH_IR_PIN_CONTROL BLDCFG_FCH_IR_PIN_CONTROL
797 #else
798 #define CFG_FCH_IR_PIN_CONTROL (BIT5 | BIT1 | BIT0)
799 #endif
800
801 #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
802 #define CFG_FCH_SD_CLOCK_CONTROL BLDCFG_FCH_SD_CLOCK_CONTROL
803 #else
804 #define CFG_FCH_SD_CLOCK_CONTROL Sd50MhzTraceCableLengthWithinSixInches
805 #endif
806
807 #ifdef BLDCFG_FCH_SCI_MAP_LIST
808 #define CFG_FCH_SCI_MAP_LIST BLDCFG_FCH_SCI_MAP_LIST
809 #else
810 #define CFG_FCH_SCI_MAP_LIST NULL
811 #endif
812
813 #ifdef BLDCFG_FCH_SATA_PHY_LIST
814 #define CFG_FCH_SATA_PHY_LIST BLDCFG_FCH_SATA_PHY_LIST
815 #else
816 #define CFG_FCH_SATA_PHY_LIST NULL
817 #endif
818
819 #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
820 #define CFG_FCH_GPIO_CONTROL_LIST BLDCFG_FCH_GPIO_CONTROL_LIST
821 #else
822 #define CFG_FCH_GPIO_CONTROL_LIST NULL
823 #endif
824
825
826 #ifdef AGESA_ENTRY_INIT_RESET
827 #if AGESA_ENTRY_INIT_RESET == TRUE
828 //
829 // Define task list for InitReset phase
830 //
831 FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = {
832 InstallFchInitResetHwAcpiP,
833 InstallFchInitResetAb,
834 InstallFchInitResetSpi,
835 InstallFchInitResetGec,
836 InstallFchInitResetHwAcpi,
837 InstallFchInitResetSata,
838 InstallFchInitResetLpc,
839 InstallFchInitResetPcib,
840 InstallFchInitResetPcie,
841 InstallFchInitResetGpp,
842 InstallFchInitResetUsb,
843 InstallFchInitResetUsbEhci,
844 InstallFchInitResetUsbOhci,
845 InstallFchInitResetUsbXhci,
846 InstallFchInitResetImc,
847 NULL
848 };
849 #endif
850 #endif
851
852 #ifdef AGESA_ENTRY_INIT_ENV
853 #if AGESA_ENTRY_INIT_ENV == TRUE
854 //
855 // Define task list for InitEnv phase
856 //
857 FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = {
858 InstallFchInitEnvHwAcpiP,
859 InstallFchInitEnvPcib,
860 InstallFchInitEnvPcie,
861 InstallFchInitEnvGpp,
862 InstallFchInitEnvIr,
863 InstallFchInitEnvHwAcpi,
864 InstallFchInitEnvSpi,
865 InstallFchInitEnvSd,
866 InstallFchInitEnvImc,
867 InstallFchInitEnvUsb,
868 InstallFchInitEnvUsbEhci,
869 InstallFchInitEnvUsbOhci,
870 InstallFchInitEnvUsbXhci,
871 InstallFchInitEnvSata,
872 InstallFchInitEnvIde,
873 InstallFchInitEnvGec,
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]874 InstallFchInitEnvAzalia,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]875 InstallFchInitEnvAb,
876 InstallFchInitEnvHwm,
877 InstallFchInitEnvGppPhaseII,
878 InstallFchInitEnvAbS,
879 NULL
880 };
881 #endif
882 #endif
883
884
885 #ifdef AGESA_ENTRY_INIT_MID
886 #if AGESA_ENTRY_INIT_MID == TRUE
887 //
888 // Define task list for InitMid phase
889 //
890 FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = {
891 InstallFchInitMidImc,
892 InstallFchInitMidUsb,
893 InstallFchInitMidUsbEhci,
894 InstallFchInitMidUsbOhci,
895 InstallFchInitMidUsbXhci,
896 InstallFchInitMidSata,
897 InstallFchInitMidIde,
898 InstallFchInitMidGec,
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]899 InstallFchInitMidAzalia,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]900 InstallFchInitMidHwm,
901 NULL
902 };
903 #endif
904 #endif
905
906 #ifdef AGESA_ENTRY_INIT_LATE
907 #if AGESA_ENTRY_INIT_LATE == TRUE
908 //
909 // Define task list for InitLate phase
910 //
911 FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = {
912 InstallFchInitLatePcie,
913 InstallFchInitLatePcib,
914 InstallFchInitLateSpi,
915 InstallFchInitLateUsb,
916 InstallFchInitLateUsbEhci,
917 InstallFchInitLateUsbOhci,
918 InstallFchInitLateUsbXhci,
919 InstallFchInitLateSata,
920 InstallFchInitLateIde,
921 InstallFchInitLateGec,
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]922 &FchTaskDummy,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]923 InstallFchInitLateImc,
924 InstallFchInitLateHwm,
925 InstallFchInitLateGpp,
926 InstallFchInitLateHwAcpi,
927 NULL
928 };
929 #endif
930 #endif
931
932
933 #ifdef AGESA_ENTRY_INIT_ENV
934 #if AGESA_ENTRY_INIT_ENV == TRUE
935 //
936 // Define task list for S3 resume before PCI phase
937 //
938 FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = {
939 InstallFchInitEnvPcie,
940 InstallFchInitEnvPcib,
941 InstallFchInitEnvGpp,
942 InstallFchInitEnvIr,
943 InstallFchInitEnvHwAcpi,
944 InstallFchInitEnvSpi,
945 InstallFchInitEnvSd,
946 InstallFchInitEnvUsb,
947 InstallFchInitEnvUsbXhci,
948 InstallFchInitEnvSata,
949 InstallFchInitEnvIde,
950 InstallFchInitEnvGec,
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]951 InstallFchInitEnvAzalia,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]952 InstallFchInitEnvAb,
953 InstallFchInitEnvGppPhaseII,
954 InstallFchInitEnvAbS,
955 NULL
956 };
957 #endif
958 #endif
959
960 #ifdef AGESA_ENTRY_INIT_LATE
961 #if AGESA_ENTRY_INIT_LATE == TRUE
962 //
963 // Define task list for S3 resume after PCI phase
964 //
965 FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = {
966 InstallFchInitLatePcie,
967 InstallFchInitLatePcib,
968 InstallFchInitLateSpi,
969 InstallFchInitLateUsb,
970 InstallFchInitLateUsbEhci,
971 InstallFchInitLateUsbOhci,
972 InstallFchInitLateUsbXhci,
973 InstallFchInitMidSata,
974 InstallFchInitMidIde,
975 InstallFchInitMidGec,
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]976 InstallFchInitMidAzalia,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]977 InstallFchInitLateSata,
978 InstallFchInitLateIde,
979 InstallFchInitLateHwAcpi,
980 InstallFchInitLateGpp,
981 InstallFchInitEnvHwm,
982 InstallFchInitLateGpp,
983 InstallFchInitLateHwm,
984 NULL
985 };
986 #endif
987 #endif
988 FCH_TASK_ENTRY *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
989
990
991#else // FCH_SUPPORT == FALSE
992 /* FCH Interface entries */
993 extern FCH_INIT CommonFchInitStub;
994
995 #define FP_FCH_INIT_RESET &CommonFchInitStub
996 #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
997 #define FP_FCH_INIT_ENV &CommonFchInitStub
998 #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
999 #define FP_FCH_INIT_MID &CommonFchInitStub
1000 #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
1001 #define FP_FCH_INIT_LATE &CommonFchInitStub
1002 #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
1003
1004 #define CFG_SMBUS0_BASE_ADDRESS 0
1005 #define CFG_SMBUS1_BASE_ADDRESS 0
1006 #define CFG_SIO_PME_BASE_ADDRESS 0
1007 #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0
1008 #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0
1009 #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0
1010 #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0
1011 #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0
1012 #define CFG_SPI_ROM_BASE_ADDRESS 0
1013 #define CFG_WATCHDOG_TIMER_BASE 0
1014 #define CFG_HPET_BASE_ADDRESS 0
1015 #define CFG_SMI_CMD_PORT_ADDRESS 0
1016 #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0
1017 #define CFG_GEC_SHADOW_ROM_BASE 0
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]1018 #define CFG_AZALIA_SSID 0
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1019 #define CFG_SMBUS_SSID 0
1020 #define CFG_IDE_SSID 0
1021 #define CFG_SATA_AHCI_SSID 0
1022 #define CFG_SATA_IDE_SSID 0
1023 #define CFG_SATA_RAID5_SSID 0
1024 #define CFG_SATA_RAID_SSID 0
1025 #define CFG_EHCI_SSID 0
1026 #define CFG_OHCI_SSID 0
1027 #define CFG_LPC_SSID 0
1028 #define CFG_SD_SSID 0
1029 #define CFG_XHCI_SSID 0
1030 #define CFG_FCH_PORT80_BEHIND_PCIB 0
1031 #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP 0
1032 #define CFG_FCH_GPP_LINK_CONFIG 0
1033 #define CFG_FCH_GPP_PORT0_PRESENT 0
1034 #define CFG_FCH_GPP_PORT1_PRESENT 0
1035 #define CFG_FCH_GPP_PORT2_PRESENT 0
1036 #define CFG_FCH_GPP_PORT3_PRESENT 0
1037 #define CFG_FCH_GPP_PORT0_HOTPLUG 0
1038 #define CFG_FCH_GPP_PORT1_HOTPLUG 0
1039 #define CFG_FCH_GPP_PORT2_HOTPLUG 0
1040 #define CFG_FCH_GPP_PORT3_HOTPLUG 0
1041
1042 #define CFG_FCH_ESATA_PORT_BITMAP 0
1043 #define CFG_FCH_IR_PIN_CONTROL 0
1044 #define CFG_FCH_SD_CLOCK_CONTROL 0
1045 #define CFG_FCH_SCI_MAP_LIST 0
1046 #define CFG_FCH_SATA_PHY_LIST 0
1047 #define CFG_FCH_GPIO_CONTROL_LIST 0
1048
1049#endif
1050
1051
1052CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
1053 FP_FCH_INIT_RESET,
1054 FP_FCH_INIT_RESET_CONSTRUCT,
1055 FP_FCH_INIT_ENV,
1056 FP_FCH_INIT_ENV_CONSTRUCT,
1057 FP_FCH_INIT_MID,
1058 FP_FCH_INIT_MID_CONSTRUCT,
1059 FP_FCH_INIT_LATE,
1060 FP_FCH_INIT_LATE_CONSTRUCT,
1061};
1062
1063#endif // _OPTION_FCH_INSTALL_H_