Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of build option: Memory |
| 6 | * |
| 7 | * Contains AMD AGESA install macros and test conditions. Output is the |
| 8 | * defaults tables reflecting the User's build options selection. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Options |
| 13 | * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $ |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _OPTION_MEMORY_INSTALL_H_ |
| 48 | #define _OPTION_MEMORY_INSTALL_H_ |
| 49 | |
| 50 | /*------------------------------------------------------------------------------- |
| 51 | * This option file is designed to be included into the platform solution install |
| 52 | * file. The platform solution install file will define the options status. |
| 53 | * Check to validate the definition |
| 54 | */ |
| 55 | |
| 56 | /*---------------------------------------------------------------------------------- |
| 57 | * FEATURE BLOCK FUNCTIONS |
| 58 | * |
| 59 | * This section defines function names that depend upon options that are selected |
| 60 | * in the platform solution install file. |
| 61 | */ |
| 62 | BOOLEAN MemFDefRet ( |
| 63 | IN OUT MEM_NB_BLOCK *NBPtr |
| 64 | ) |
| 65 | { |
| 66 | return FALSE; |
| 67 | } |
| 68 | |
| 69 | BOOLEAN MemMDefRet ( |
| 70 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 71 | ) |
| 72 | { |
| 73 | return TRUE; |
| 74 | } |
| 75 | |
| 76 | BOOLEAN MemMDefRetFalse ( |
| 77 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 78 | ) |
| 79 | { |
| 80 | return FALSE; |
| 81 | } |
| 82 | |
| 83 | /* -----------------------------------------------------------------------------*/ |
| 84 | /** |
| 85 | * |
| 86 | * |
| 87 | * This function initializes the northbridge block for dimm identification translator |
| 88 | * |
| 89 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 90 | * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT |
| 91 | * @param[in,out] NodeID - ID of current node to construct |
| 92 | * @return TRUE - This is the correct constructor for the targeted node. |
| 93 | * @return FALSE - This isn't the correct constructor for the targeted node. |
| 94 | */ |
| 95 | BOOLEAN MemNIdentifyDimmConstructorRetDef ( |
| 96 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 97 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 98 | IN UINT8 NodeID |
| 99 | ) |
| 100 | { |
| 101 | return FALSE; |
| 102 | } |
| 103 | /*---------------------------------------------------------------------------------- |
| 104 | * TABLE FEATURE BLOCK FUNCTIONS |
| 105 | * |
| 106 | * This section defines function names that depend upon options that are selected |
| 107 | * in the platform solution install file. |
| 108 | */ |
| 109 | UINT8 MemFTableDefRet ( |
| 110 | IN OUT MEM_TABLE_ALIAS **MTPtr |
| 111 | ) |
| 112 | { |
| 113 | return 0; |
| 114 | } |
| 115 | /*---------------------------------------------------------------------------------- |
| 116 | * FEATURE S3 BLOCK FUNCTIONS |
| 117 | * |
| 118 | * This section defines function names that depend upon options that are selected |
| 119 | * in the platform solution install file. |
| 120 | */ |
| 121 | BOOLEAN MemFS3DefConstructorRet ( |
| 122 | IN OUT VOID *S3NBPtr, |
| 123 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 124 | IN UINT8 NodeID |
| 125 | ) |
| 126 | { |
| 127 | return TRUE; |
| 128 | } |
| 129 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 130 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 131 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 132 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 133 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; |
| 134 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON |
| 135 | #else |
| 136 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet |
| 137 | #endif |
| 138 | #else |
| 139 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet |
| 140 | #endif |
| 141 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 142 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; |
| 143 | #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON |
| 144 | #else |
| 145 | #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef |
| 146 | #endif |
| 147 | #endif |
| 148 | |
| 149 | /*---------------------------------------------------------------------------------- |
| 150 | * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS |
| 151 | * |
| 152 | *---------------------------------------------------------------------------------- |
| 153 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 154 | #define MEM_NB_SUPPORT_ON |
| 155 | #define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } |
| 156 | |
| 157 | #if (AGESA_ENTRY_INIT_POST == TRUE) |
| 158 | /*---------------------------------------------------------------------------------- |
| 159 | * FLOW CONTROL FUNCTION |
| 160 | * |
| 161 | * This section selects the function that controls the memory initialization sequence |
| 162 | * based upon the number of processor families that the BIOS will support. |
| 163 | */ |
| 164 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 165 | extern MEM_FLOW_CFG MemMFlowDef; |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 166 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 167 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 168 | extern MEM_FLOW_CFG MemMFlowON; |
| 169 | #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, |
| 170 | #else |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 171 | #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, |
| 172 | #endif |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 173 | |
| 174 | MEM_FLOW_CFG* memFlowControlInstalled[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 175 | MEM_MAIN_FLOW_CONTROL_PTR_ON |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 176 | NULL |
| 177 | }; |
| 178 | |
| 179 | #if (OPTION_ONLINE_SPARE == TRUE) |
| 180 | extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; |
| 181 | #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare |
| 182 | extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; |
| 183 | #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare |
| 184 | #else |
| 185 | #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet |
| 186 | #define MEM_FEATURE_ONLINE_SPARE MemFDefRet |
| 187 | #endif |
| 188 | |
| 189 | #if (OPTION_MEM_RESTORE == TRUE) |
| 190 | extern OPTION_MEM_FEATURE_MAIN MemMContextSave; |
| 191 | extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; |
| 192 | #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave |
| 193 | #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore |
| 194 | #else |
| 195 | #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet |
| 196 | #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse |
| 197 | #endif |
| 198 | |
| 199 | #if (OPTION_BANK_INTERLEAVE == TRUE) |
| 200 | extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; |
| 201 | #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks |
| 202 | extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; |
| 203 | #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks |
| 204 | #else |
| 205 | #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet |
| 206 | #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet |
| 207 | #endif |
| 208 | |
| 209 | #if (OPTION_NODE_INTERLEAVE == TRUE) |
| 210 | extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; |
| 211 | #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes |
| 212 | extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; |
| 213 | extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; |
| 214 | #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes |
| 215 | #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes |
| 216 | #else |
| 217 | #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet |
| 218 | #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet |
| 219 | #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet |
| 220 | #endif |
| 221 | |
| 222 | #if (OPTION_DCT_INTERLEAVE == TRUE) |
| 223 | extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; |
| 224 | #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels |
| 225 | #else |
| 226 | #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet |
| 227 | #endif |
| 228 | |
| 229 | #if (OPTION_ECC == TRUE) |
| 230 | extern OPTION_MEM_FEATURE_MAIN MemMEcc; |
| 231 | #define MEM_MAIN_FEATURE_ECC MemMEcc |
| 232 | extern OPTION_MEM_FEATURE_NB MemFCheckECC; |
| 233 | extern OPTION_MEM_FEATURE_NB MemFInitECC; |
| 234 | #define MEM_FEATURE_CK_ECC MemFCheckECC |
| 235 | #define MEM_FEATURE_ECC MemFInitECC |
| 236 | #define MEM_FEATURE_ECCX8 MemMDefRet |
| 237 | #else |
| 238 | #define MEM_MAIN_FEATURE_ECC MemMDefRet |
| 239 | #define MEM_FEATURE_CK_ECC MemFDefRet |
| 240 | #define MEM_FEATURE_ECC MemFDefRet |
| 241 | #define MEM_FEATURE_ECCX8 MemMDefRet |
| 242 | #endif |
| 243 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 244 | extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; |
| 245 | #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr |
| 246 | |
| 247 | #if (OPTION_DMI == TRUE) |
| 248 | #if (OPTION_DDR3 == TRUE) |
| 249 | extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; |
| 250 | #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 |
| 251 | #else |
| 252 | extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; |
| 253 | #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 |
| 254 | #endif |
| 255 | #else |
| 256 | #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet |
| 257 | #endif |
| 258 | |
| 259 | #if (OPTION_DDR3 == TRUE) |
| 260 | extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; |
| 261 | extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; |
| 262 | extern OPTION_MEM_FEATURE_NB MemFLvDdr3; |
| 263 | #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal |
| 264 | #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 |
| 265 | #define MEM_FEATURE_LVDDR3 MemFLvDdr3 |
| 266 | #else |
| 267 | #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet |
| 268 | #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet |
| 269 | #define MEM_FEATURE_LVDDR3 MemFDefRet |
| 270 | #endif |
| 271 | |
| 272 | extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; |
| 273 | #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion |
| 274 | |
| 275 | extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; |
| 276 | #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc |
| 277 | |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 278 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 279 | #if (OPTION_PARALLEL_TRAINING == TRUE) |
| 280 | extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; |
| 281 | #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining |
| 282 | #else |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 283 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 284 | #endif |
| 285 | |
| 286 | #if (OPTION_DIMM_EXCLUDE == TRUE) |
| 287 | extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; |
| 288 | #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM |
| 289 | extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; |
| 290 | #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM |
| 291 | #else |
| 292 | #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet |
| 293 | #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet |
| 294 | #endif |
| 295 | |
| 296 | /*---------------------------------------------------------------------------------- |
| 297 | * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS |
| 298 | * |
| 299 | *---------------------------------------------------------------------------------- |
| 300 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 301 | #if OPTION_DDR3 == TRUE |
| 302 | extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; |
| 303 | #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, |
| 304 | #if (OPTION_HW_DRAM_INIT == TRUE) |
| 305 | extern MEM_TECH_FEAT MemTDramInitHw; |
| 306 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw |
| 307 | #else |
| 308 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef |
| 309 | #endif |
| 310 | #if (OPTION_SW_DRAM_INIT == TRUE) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 311 | // extern MEM_TECH_FEAT MemTDramInitSw3; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 312 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 |
| 313 | #else |
| 314 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef |
| 315 | #endif |
| 316 | #else |
| 317 | #define MEM_TECH_CONSTRUCTOR_DDR3 |
| 318 | #endif |
| 319 | |
| 320 | /*--------------------------------------------------------------------------------------------------- |
| 321 | * FEATURE BLOCKS |
| 322 | * |
| 323 | * This section instantiates a feature block structure for each memory controller installed |
| 324 | * by the platform solution install file. |
| 325 | *--------------------------------------------------------------------------------------------------- |
| 326 | */ |
| 327 | |
| 328 | /*--------------------------------------------------------------------------------------------------- |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 329 | * ONTARIO FEATURE BLOCK |
| 330 | *--------------------------------------------------------------------------------------------------- |
| 331 | */ |
| 332 | #if (OPTION_MEMCTLR_ON == TRUE) |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 333 | #if OPTION_DDR3 |
| 334 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 335 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 336 | #endif |
| 337 | |
| 338 | #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) |
| 339 | extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; |
| 340 | #undef MEM_TECH_FEATURE_CPG |
| 341 | #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb |
| 342 | #else |
| 343 | #undef MEM_TECH_FEATURE_CPG |
| 344 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 345 | #endif |
| 346 | |
| 347 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 348 | extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; |
| 349 | #undef MEM_TECH_FEATURE_HWRXEN |
| 350 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 351 | #else |
| 352 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 353 | #undef MEM_TECH_FEATURE_HWRXEN |
| 354 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 355 | #endif |
| 356 | |
| 357 | #undef MEM_MAIN_FEATURE_TRAINING |
| 358 | #undef MEM_FEATURE_TRAINING |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 359 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 360 | extern OPTION_MEM_FEATURE_NB MemFStandardTraining; |
| 361 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 362 | |
| 363 | #if (OPTION_EARLY_SAMPLES == TRUE) |
| 364 | extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; |
| 365 | #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON |
| 366 | #else |
| 367 | #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet |
| 368 | #endif |
| 369 | |
| 370 | MEM_FEAT_BLOCK_NB MemFeatBlockOn = { |
| 371 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 372 | MemFDefRet, |
| 373 | MEM_FEATURE_BANK_INTERLEAVE, |
| 374 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 375 | MemFDefRet, |
| 376 | MemFDefRet, |
| 377 | MemFDefRet, |
| 378 | MemFDefRet, |
| 379 | MemFDefRet, |
| 380 | MemFDefRet, |
| 381 | MEM_FEATURE_TRAINING, |
| 382 | MEM_FEATURE_LVDDR3, |
| 383 | MEM_FEATURE_ONDIMMTHERMAL, |
| 384 | MEM_TECH_FEATURE_DRAMINIT, |
| 385 | MEM_FEATURE_DIMM_EXCLUDE, |
| 386 | MEM_EARLY_SAMPLE_SUPPORT, |
| 387 | MEM_TECH_FEATURE_CPG, |
| 388 | MEM_TECH_FEATURE_HWRXEN |
| 389 | }; |
| 390 | |
| 391 | #undef MEM_NB_SUPPORT_ON |
| 392 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; |
| 393 | extern MEM_INITIALIZER MemNInitDefaultsON; |
| 394 | #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, |
| 395 | |
| 396 | #endif // OPTION_MEMCTRL_ON |
| 397 | |
| 398 | /*--------------------------------------------------------------------------------------------------- |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 399 | * MAIN FEATURE BLOCK |
| 400 | *--------------------------------------------------------------------------------------------------- |
| 401 | */ |
| 402 | MEM_FEAT_BLOCK_MAIN MemFeatMain = { |
| 403 | MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, |
| 404 | MEM_MAIN_FEATURE_TRAINING, |
| 405 | MEM_MAIN_FEATURE_DIMM_EXCLUDE, |
| 406 | MEM_MAIN_FEATURE_ONLINE_SPARE, |
| 407 | MEM_MAIN_FEATURE_NODE_INTERLEAVE, |
| 408 | MEM_MAIN_FEATURE_ECC, |
| 409 | MEM_MAIN_FEATURE_MEM_CLEAR, |
| 410 | MEM_MAIN_FEATURE_MEM_DMI, |
| 411 | MEM_MAIN_FEATURE_LVDDR3, |
| 412 | MEM_MAIN_FEATURE_UMAALLOC, |
| 413 | MEM_MAIN_FEATURE_MEM_SAVE, |
| 414 | MEM_MAIN_FEATURE_MEM_RESTORE |
| 415 | }; |
| 416 | |
| 417 | |
| 418 | /*--------------------------------------------------------------------------------------------------- |
| 419 | * Technology Training SPECIFIC CONFIGURATION |
| 420 | * |
| 421 | * |
| 422 | *--------------------------------------------------------------------------------------------------- |
| 423 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 424 | |
| 425 | #if OPTION_MEMCTLR_ON |
| 426 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 427 | #if OPTION_DDR3 |
| 428 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 429 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 430 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 431 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 |
| 432 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 433 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 434 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 435 | #else |
| 436 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 437 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 438 | #endif |
| 439 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 440 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 441 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 442 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 443 | #else |
| 444 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 445 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 446 | #endif |
| 447 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 448 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 449 | #else |
| 450 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 451 | #endif |
| 452 | #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 |
| 453 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 454 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 455 | #else |
| 456 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 457 | #endif |
| 458 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 459 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 460 | #else |
| 461 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 462 | #endif |
| 463 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 464 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 465 | #else |
| 466 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 467 | #endif |
| 468 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 469 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 470 | #else |
| 471 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 472 | #endif |
| 473 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { |
| 474 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 475 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 476 | TECH_TRAIN_SW_WL_DDR3, |
| 477 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 478 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 479 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 480 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 481 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 482 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 483 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 484 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 485 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 486 | TECH_TRAIN_MAX_RD_LAT_DDR3 |
| 487 | }; |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 488 | // extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 489 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 490 | // extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 491 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, |
| 492 | #else |
| 493 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 494 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 495 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 496 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 497 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 498 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 499 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 500 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 501 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 502 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 503 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 504 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 505 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 506 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 507 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 508 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 509 | #endif |
| 510 | #else |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 511 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 512 | #endif |
| 513 | |
| 514 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 515 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 516 | MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 517 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 518 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_END |
| 519 | }; |
| 520 | /*--------------------------------------------------------------------------------------------------- |
| 521 | * NB TRAINING FLOW CONTROL |
| 522 | * |
| 523 | * |
| 524 | *--------------------------------------------------------------------------------------------------- |
| 525 | */ |
Kyösti Mälkki | 5023c32 | 2018-05-06 10:21:34 +0300 | [diff] [blame] | 526 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 527 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 528 | OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control |
| 529 | NB_TRAIN_FLOW_DDR2, |
| 530 | NB_TRAIN_FLOW_DDR3, |
| 531 | }; |
| 532 | /*--------------------------------------------------------------------------------------------------- |
| 533 | * TECHNOLOGY BLOCK |
| 534 | * |
| 535 | * |
| 536 | *--------------------------------------------------------------------------------------------------- |
| 537 | */ |
| 538 | MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 539 | MEM_TECH_CONSTRUCTOR_DDR3 |
| 540 | NULL |
| 541 | }; |
| 542 | /*--------------------------------------------------------------------------------------------------- |
| 543 | * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION |
| 544 | * |
| 545 | * |
| 546 | *--------------------------------------------------------------------------------------------------- |
| 547 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 548 | |
| 549 | #if OPTION_MEMCTLR_ON |
| 550 | #if OPTION_UDIMMS |
| 551 | #if OPTION_DDR3 |
| 552 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, |
| 553 | #else |
| 554 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 555 | #endif |
| 556 | #else |
| 557 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 558 | #endif |
| 559 | #if OPTION_SODIMMS |
| 560 | #if OPTION_DDR3 |
| 561 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, |
| 562 | #else |
| 563 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 564 | #endif |
| 565 | #else |
| 566 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 567 | #endif |
| 568 | #else |
| 569 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 570 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 571 | #endif |
Jacob Garber | ab734d8 | 2020-02-18 23:08:07 -0700 | [diff] [blame] | 572 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 573 | PLAT_SP_ON_FF_SDIMM3 |
| 574 | PLAT_SP_ON_FF_UDIMM3 |
| 575 | NULL |
| 576 | }; |
| 577 | |
| 578 | /*--------------------------------------------------------------------------------------------------- |
| 579 | * PLATFORM-SPECIFIC CONFIGURATION |
| 580 | * |
| 581 | * |
| 582 | *--------------------------------------------------------------------------------------------------- |
| 583 | */ |
| 584 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 585 | #if OPTION_MEMCTLR_ON |
| 586 | #if OPTION_UDIMMS |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 587 | #if OPTION_DDR3 |
| 588 | #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, |
| 589 | #else |
| 590 | #define PSC_ON_UDIMM_DDR3 |
| 591 | #endif |
| 592 | #endif |
| 593 | #if OPTION_RDIMMS |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 594 | #if OPTION_DDR3 |
| 595 | #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, |
| 596 | #else |
| 597 | #define PSC_ON_RDIMM_DDR3 |
| 598 | #endif |
| 599 | #endif |
| 600 | #if OPTION_SODIMMS |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 601 | #if OPTION_DDR3 |
| 602 | #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, |
| 603 | #else |
| 604 | #define PSC_ON_SODIMM_DDR3 |
| 605 | #endif |
| 606 | #endif |
| 607 | #endif |
| 608 | |
| 609 | /*---------------------------------------------------------------------- |
| 610 | * DEFAULT PSCFG DEFINITIONS |
| 611 | * |
| 612 | *---------------------------------------------------------------------- |
| 613 | */ |
| 614 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 615 | #ifndef PSC_ON_UDIMM_DDR3 |
| 616 | #define PSC_ON_UDIMM_DDR3 |
| 617 | #endif |
| 618 | #ifndef PSC_ON_RDIMM_DDR3 |
| 619 | #define PSC_ON_RDIMM_DDR3 |
| 620 | #endif |
| 621 | #ifndef PSC_ON_SODIMM_DDR3 |
| 622 | #define PSC_ON_SODIMM_DDR3 |
| 623 | #endif |
| 624 | |
| 625 | MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 626 | PSC_ON_UDIMM_DDR3 |
| 627 | PSC_ON_RDIMM_DDR3 |
| 628 | PSC_ON_SODIMM_DDR3 |
| 629 | NULL |
| 630 | }; |
| 631 | CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 632 | // #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES |
| 633 | // #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES |
| 634 | // #endif |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 635 | |
| 636 | /*--------------------------------------------------------------------------------------------------- |
| 637 | * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION |
| 638 | * |
| 639 | * |
| 640 | *--------------------------------------------------------------------------------------------------- |
| 641 | */ |
| 642 | #define MEM_PSC_FLOW_BLOCK_END NULL |
| 643 | #define PSC_TBL_END NULL |
| 644 | #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue |
| 645 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 646 | |
| 647 | MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 648 | MEM_PSC_FLOW_BLOCK_END |
| 649 | }; |
| 650 | |
| 651 | /*--------------------------------------------------------------------------------------------------- |
| 652 | * |
| 653 | * LRDIMM CONTROL |
| 654 | * |
| 655 | *--------------------------------------------------------------------------------------------------- |
| 656 | */ |
| 657 | #if (OPTION_LRDIMMS == TRUE) |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 658 | #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 659 | #else //#if (OPTION_LRDIMMS == FALSE) |
| 660 | #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef |
| 661 | #endif |
| 662 | MEM_TECH_LRDIMM memLrdimmSupported = { |
| 663 | MEM_TECH_LRDIMM_STRUCT_VERSION, |
| 664 | MEM_TECH_FEATURE_LRDIMM_INIT |
| 665 | }; |
| 666 | #else |
| 667 | /*--------------------------------------------------------------------------------------------------- |
| 668 | * MAIN FLOW CONTROL |
| 669 | * |
| 670 | * |
| 671 | *--------------------------------------------------------------------------------------------------- |
| 672 | */ |
| 673 | MEM_FLOW_CFG* memFlowControlInstalled[] = { |
| 674 | NULL |
| 675 | }; |
| 676 | /*--------------------------------------------------------------------------------------------------- |
| 677 | * NB TRAINING FLOW CONTROL |
| 678 | * |
| 679 | * |
| 680 | *--------------------------------------------------------------------------------------------------- |
| 681 | */ |
| 682 | OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control |
Joe Moore | a608dd8 | 2020-01-04 13:33:34 -0700 | [diff] [blame] | 683 | NULL, |
| 684 | NULL, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 685 | }; |
| 686 | /*--------------------------------------------------------------------------------------------------- |
| 687 | * DEFAULT TECHNOLOGY BLOCK |
| 688 | * |
| 689 | * |
| 690 | *--------------------------------------------------------------------------------------------------- |
| 691 | */ |
| 692 | MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed |
| 693 | NULL |
| 694 | }; |
| 695 | |
| 696 | /*--------------------------------------------------------------------------------------------------- |
| 697 | * DEFAULT TECHNOLOGY MAP |
| 698 | * |
| 699 | * |
| 700 | *--------------------------------------------------------------------------------------------------- |
| 701 | */ |
| 702 | UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; |
| 703 | |
| 704 | /*--------------------------------------------------------------------------------------------------- |
| 705 | * DEFAULT MAIN FEATURE BLOCK |
| 706 | *--------------------------------------------------------------------------------------------------- |
| 707 | */ |
| 708 | MEM_FEAT_BLOCK_MAIN MemFeatMain = { |
Kyösti Mälkki | defbdcf | 2016-04-19 15:17:50 +0300 | [diff] [blame] | 709 | 0 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 710 | }; |
| 711 | |
| 712 | /*--------------------------------------------------------------------------------------------------- |
| 713 | * DEFAULT NORTHBRIDGE SUPPORT LIST |
| 714 | * |
| 715 | * |
| 716 | *--------------------------------------------------------------------------------------------------- |
| 717 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 718 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 719 | #undef MEM_NB_SUPPORT_ON |
| 720 | #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, |
| 721 | #endif |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 722 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 723 | /*--------------------------------------------------------------------------------------------------- |
| 724 | * DEFAULT Technology Training |
| 725 | * |
| 726 | * |
| 727 | *--------------------------------------------------------------------------------------------------- |
| 728 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 729 | #if OPTION_DDR3 |
| 730 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { |
Kyösti Mälkki | defbdcf | 2016-04-19 15:17:50 +0300 | [diff] [blame] | 731 | 0 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 732 | }; |
| 733 | MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { |
Stefan Reinauer | 8e6bb80 | 2017-06-25 05:46:56 +0200 | [diff] [blame] | 734 | { 0 } |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 735 | }; |
| 736 | #endif |
Kyösti Mälkki | ba4e695 | 2017-08-31 15:17:36 +0300 | [diff] [blame] | 737 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 738 | /*--------------------------------------------------------------------------------------------------- |
| 739 | * DEFAULT Platform Specific list |
| 740 | * |
| 741 | * |
| 742 | *--------------------------------------------------------------------------------------------------- |
| 743 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 744 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 745 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { |
| 746 | NULL |
| 747 | }; |
| 748 | #endif |
| 749 | /*---------------------------------------------------------------------- |
| 750 | * DEFAULT PSCFG DEFINITIONS |
| 751 | * |
| 752 | *---------------------------------------------------------------------- |
| 753 | */ |
| 754 | MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { |
| 755 | NULL |
| 756 | }; |
| 757 | |
| 758 | /*---------------------------------------------------------------------- |
| 759 | * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION |
| 760 | * |
| 761 | *---------------------------------------------------------------------- |
| 762 | */ |
| 763 | MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { |
| 764 | NULL |
| 765 | }; |
| 766 | |
| 767 | MEM_TECH_LRDIMM memLrdimmSupported = { |
| 768 | MEM_TECH_LRDIMM_STRUCT_VERSION, |
| 769 | NULL |
| 770 | }; |
| 771 | #endif |
| 772 | |
| 773 | /*--------------------------------------------------------------------------------------------------- |
| 774 | * NORTHBRIDGE SUPPORT LIST |
| 775 | * |
| 776 | * |
| 777 | *--------------------------------------------------------------------------------------------------- |
| 778 | */ |
| 779 | MEM_NB_SUPPORT memNBInstalled[] = { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 780 | MEM_NB_SUPPORT_ON |
| 781 | MEM_NB_SUPPORT_END |
| 782 | }; |
| 783 | |
| 784 | #endif // _OPTION_MEMORY_INSTALL_H_ |